Hardware Reference
In-Depth Information
Even for the largest circuits, an average rank better than 1.2 was obtained, and
the real culprit was most often on top of the list. Only in cases where distinguishing
patterns could not be generated and the faults seemed to be equivalent, multiple
trials were required.
If volume diagnosis is performed, the test set cannot be enhanced and only a lim-
ited number of failing patterns is observed. By storing eight failing pattern outputs
at maximum, the method described above puts the real culprit in average at rank
1.5 within the candidate fault list. This value is highly sufficient for deciding about
further adaptive diagnosis in a second step.
The conditions for single stuck-at faults are rather simple, and diagnosis of more
complex single line faults is more challenging. An example which fits for both logic
debug and complex CMOS cells is the analysis of gates of a wrong type. For in-
stance, the exchange of an a
D
b OR c by an a
D
b AND c is described by the
CLF a
˚
Œb
˚
c. Experiments are reported about randomly changing the gate type
while the rank of the real culprit is still better than 1.5 on average.
Similar results are known, if timing has to be considered in the activating condi-
tion of the CLF. An example is crosstalk fault as described above where the rank of
the real culprits still remained at the top level.
5.5.2
Multiple Line Defects
If multiple lines are faulty, the corresponding fault effects may mask each other.
As a consequence, predictions and mispredictions on an actual CLF may be af-
fected in the presence of other active CLFs. Yet, it is known that test sets for single
stuck-at faults are able to detect a large part of multiple stuck-at faults. The same
reasoning does also hold for CLFs, however, it is not any more true that the (uncon-
ditional) stuck-at fault at one of the defect lines always explains the highest number
of errors.
The reasonings described above form just a heuristic and still works in a rather
efficient way as evidenced by the results reported. The 4-way bridges discussed
above affect two lines, and just by looking only into 8 failing output patterns the
algorithm described above points to the defect region with an average rank of 2.
5.6
Summary
Faults in circuits, those implemented in modern technology, show a more and more
complex behavior. Diagnosis algorithms cannot assume any more a simplified fault
model but have to do both locating the flaws in the structure and layout and extract-
ing the faulty behavior at these lines. The chapter introduced a method to model
faulty behavior of defective lines sufficiently precise for debug and diagnosis.
