Fault Modeling for Simulation and ATPG - Models in Hardware Testing - page 119

table construction, consumes below 2 s for ISCAS circuits and up to three minutes
for NXP circuits. The RBF coverage tends to exceed the stuck-at fault coverage of
the same test set. The average RBF simulation time is some 19 times larger than
stuck-at simulation time. This is competitive because the number of stuck-at faults
is approximately five times smaller than the number of RBFs. Note that the number
of sections and thus the number of the simulated equivalent multiple stuck-at faults
is larger because an RBF has multiple sections (we observed the average number of
sections per RBF being slightly above 3).

4.3.5 Summary

Sectioning-based resistive bridging fault simulation produces the same results as the
interval-based simulation from the last section, yet the computation is accelerated by
several orders of magnitude. Moreover, any improvements in the (multiple) stuck-
at simulation engine are leveraged immediately. The main reason for this gain in
efficiency is the mapping of a continuous problem (detectability of a fault as a func-
tion of its resistance) to discrete objects, i.e., sections, which can be manipulated by
efficient discrete algorithms.

4.4 Automatic Test Pattern Generation

We have previously seen that, for a given RBF f , the circuit behavior on the logical
level is identical for all defect resistances R sh belonging to the same section [R i 1 ,
R i ]. This implies that a test pattern which detects the fault for one resistance from
the section covers the entire section. We first propose procedure gen test which
finds a test pattern for an RBF restricted to a section. This procedure is called itera-
tively to cover all sections for all faults. RBF simulation is used to identify faults and
sections covered by the patterns generated so far. Furthermore, gen test can prove
that an RBF restricted to a section is undetectable. Identification of all undetectable
sections yields the global analogue detectability interval G-ADI which is required
to calculate the accurate fault coverage G-FC .

4.4.1 Test Generation for a Section

Procedure gen test takes a circuit CKT with n inputs and p outputs, a resistive
bridging fault f and a section S WD ŒR i 1 ;R i of fault f as inputs, and produces
a test pattern which detects all resistive bridging defects described by f having
resistances within section S , i.e., between R i 1 and R i . The procedure is based
on constructing a Boolean satisfiability instance and calling a SAT solver to obtain