Hardware Reference
In-Depth Information
Chapter 4
Fault Modeling for Simulation and ATPG
Bernd Becker and Ilia Polian
Abstract
Fault simulation and ATPG are core algorithms in the context of digital
hardware test. Their deployment for resistive fault models is challenging as the be-
havior of the defective circuit depends on the defect resistance and the number of
possible resistances is infinite. In this chapter, we show that efficient fault simu-
lation and ATPG algorithms are feasible for resistive bridging faults. Application
of the algorithms to multi-million gate industrial circuits without sacrificing accu-
racy is demonstrated. We cover in detail the abstraction mechanisms required for
the algorithms, the algorithms themselves and their optimizations. We also indicate
how a resistive bridging fault framework can be employed for problems outside the
classical test development.
Keywords
Resistive defects
Fault simulation
Automatic test pattern generation
Fault simulation and automatic test pattern generation (ATPG) are essential steps
of test preparation for digital integrated circuits (ICs). Fault simulation is used to
estimate the quality of an existing collection of test patterns (test set), i.e., its ability
to identify a failing chip. Fault simulation is also useful to evaluate the efficiency
of fault-tolerance mechanisms in dependable computer architectures described in
Chapter
8
of this topic. ATPG is used to produce a high-quality test set. Typical
ATPG algorithms work iteratively: they generate patterns, run fault simulation to
determine whether the quality of the test set obtained so far is sufficient, and produce
more patterns if required.
Both fault simulation and ATPG are defined with respect to a
fault model
.A
fault
is a
model
of a defect which could have occurred during the manufacturing of an
IC. An instance of a defect is a conducting particle leading to a bridge between an
interconnect and a neighboring power rail. An instance of a fault is a logic signal line
connected to an output of a logic gate being permanently set to logic-1 regardless of
the value which the gate attempts to impose on the line (
stuck-at-1
fault).
Stuck-at-0
faults are defined symmetrically.
) and I. Polian
Albert-Ludwigs-University of Freiburg, Germany
B. Becker (
