Digital Signal Processing Reference
In-Depth Information
ω
3dB
of a multistage amplifier,
norm
a
lized to the
b
andwi
d
th of
o
ne sta
g
e.
[%]
90
80
70
60
50
40
30
20
2
3
4
5
6
7
8
9
Number of stages
Figure A.2.
Bandwidth reduction in a multistage amplifier. For example, in a cas-
caded amplifier with three equal gain elements, the cut-off frequency
drops to 50% of that of a single stage amplifier.
stage. As shown in Figure A.2, the bandwidth of a cascaded amplifier is se-
riously degraded for an increasing number of gain stages (A.14):
2
n
1
r
ds
C
gs
·
ω
3dB, n-stage
=
−
1
(A.14)
For example, suppose a deep submicron technology (e.g. 130 nm) with an
f
T
of
100 GHz. The low frequency gain of a single transistor is 30 dB. The bandwidth
of one single ideal stage (Figure A.1) is thus 3 GHz. For a three-stage amplifier
however, the bandwidth has already decreased to 1
.
5 GHz, even without taking
the wiring or load capacitance at the output into account. In addition, both the
current gain and the location of the 3 dB frequency point are defined by
r
ds
and
C
gs
. The value of these transistor parameters strongly depends on the process
characteristics. It is advised against using them as a reliable or critical design
constant.
The frequency performance of the multistage amplifier can be increased by
applying a feedback path which spans over one or more gain stages: assuming
that stability is correctly taken into account, gain can be traded for bandwidth
within certain boundaries. Consider the feedback amplifier in Figure A.3. The
transfer characteristic can be calculated as (A.15):
A
A
cl
=
,
(A.15)
1
+
AH
where
A
is the forward gain of the amplifier and
H
is the feedback factor, of
which the power gain
2
|
H
|
is usually smaller than unity. The transfer function
