Digital Signal Processing Reference
In-Depth Information
g m
I bias
C gs
W
I bias
f T
constant , for fixed V gs
V T
(A.12)
The results presented here should not be surprising after all, since scaling a
transistor's width W without changing the length L basically boils down to
placing several independent transistors in parallel. Intuitively one can see that
connecting those transistors in parallel should have no effect on gain or on fre-
quency performance. To conclude this introduction, Table A.1 summarizes the
considerations one should make during the design of an analog most ampli-
fier. Although the deductions were made using the simplified model of a mos
transistor in the strong inversion saturation region, the general idea remains
valid for characteristics anywhere between a quadratic and a linear current-
voltage transistor model.
Dc-gain ( g m r ds )
Cut-off frequency ( f T )
1
V gs
Fixed I bias , variable V gst
V gs V T
V T
Fixed V gst , variable I bias
Constant
Constant
Table A.1.
Correlation between biasing and small-signal performance of a mos
transistor in the strong inversion saturation region.
Remark that for a fixed overdrive voltage V gs
V T , both the dc and the high
frequency performance of the mos transistor are independent of the power
consumption. Only technological parameters such as oxide thickness ( t ox ), di-
electric constant ( ox ) and minimal gate length ( L min ) define the performance
limits of a certain cmos process.
A.1
Feedback amplifiers
Despite the good low frequency gain performance, the multistage current am-
plifier introduced in Figure A.1 is not suited for high frequency applications.
This is because the location of the 3 dB cut-off frequency of a single stage is
defined by r ds and C gs . The overall transfer function of a n identical cascaded
gain stages is given by (A.13):
n
g m r ds
A(jω)
=
(A.13)
1
+
jωr ds C gs
It follows that, for a system with n ( > 1) multiple coincident poles, the 3 dB
bandwidth ( ω 3dB ) does not correspond with the frequency pole of a single
 
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