Digital Signal Processing Reference
In-Depth Information
inverse (Figure 3.4, p. 53), the approximate number of complex multiplication
operations for each issr loop is given by Equation (6.4) [Coo93]:
2
n
# iq-multiplications
/
issr loop
=
2
·
log
2
(n)
,
(6.4)
where
n
is the length of the symbol vector at the input of the issr loop. For a
symbol vector length of
n
=
1
,
024 qpsk samples, this leads to a number of
10
3
complex multiplications, for each run of the issr algorithm (i.e. 10
iterations). This boils down to a number of 5 complex multiplications/bit per
issr iteration or 50 complex multiplications for each decoded bit (10 itera-
tions). This value is very low compared to the complexity of a Turbo decoder
basedontheapp algorithm [Bah74], which requires about 192 multiplications
per decoded bit, per iteration [Pin01].
Finally, some additional research may be necessary to address the problem of
interfacing the chip with the outside world. The wideband nature of the wide-
band signals that is so typical to wideband communication systems causes sig-
nificant reflection and termination problems in a wire-bonded chip. This issue
was already brought to the attention of the reader in Figure 6.4, which shows
a decreasing trend line in the sensitivity of the receiver for increasing frequen-
cies. Using a flip-chip technique may reduce the degradation caused by the
parasitic inductance of the bonding wires. However, extending the microstrip
lines further down to the chip level will cost a lot chip area, because of the
minimal width of the microstrip traces.
102
·
