Digital Signal Processing Reference
In-Depth Information
Suggestions for continued research
Although Chapter 6 describes the implementation details and measurement
results of a pulse-based receive unit, still a lot of work needs to be done be-
fore all pieces can be assembled into a ready-to-use system. First of all, the
front-end described in Chapter 6 only includes one single receive unit, while
several of such units are working in parallel for the pulse-based radio system as
described in Chapter 5. This brings some challenging problems to the surface,
since the signal power of a single antenna is then split over the input stages
of multiple receiver units. If all units share the same physical antenna, a low-
noise preamplifier may be required to compensate for the inevitable reduction
in signal power available to each receive unit. Remember from Section 6.3 that
the lna is exposed to the full interferer power at the input of the receiver, so
this may cause problems in a channel with strong blocker levels.
Furthermore, the pulse-based radio principle, as described in Chapter 5, still
requires some additional effort in the area of digital signal processing in the
back-end section. The computational costs of the issr algorithm in terms of
hardware and energy consumption were ignored in the high-level description
of Chapter 3, since the exact figure depends on a number of design-time de-
cisions. This includes, for example, the trade-off between the degree of serial
computing and parallelism in the dft-transform of the issr algorithm. How-
ever, some preliminary calculations show that the cost of issr is fairly low,
compared to the amount of processing power required by a Viterbi decoder or
a Turbo coding system.
A summary of the parameters that were used to support this statement can be
found in Table 6.1. During the simulations in Chapter 3, the number of iter-
ations was varied between 4 and 100 issr loops. A nominal number of 10
iterations and a vector length of
n
1
,
024 symbol samples (Figure 3.6, p. 56)
were considered as the indicative numbers for the calculations. The computa-
tional cost of issr is determined by the number of multiplications, which is
the most expensive arithmetic operation. Under the assumption that the effi-
cient fast Fourier transform (fft) is being used to calculate the dft and its
=
Number of issr loops :
4
...
100 (nominal: 10 loops)
Cooley-Tukey fft (
n
=
1
,
024 symbols) :
n/
2
·
log
2
(n)
=
5
,
120 i/q-mult.
·
# i/q-multiplications per issr iteration :
2
5
,
120 approx.
# i/q-mult. per qpsk sample, per loop :
2
·
5
,
120
/n
=
10
# i/q-mult. per bit, per loop :
2
·
5
,
120
/n/
2
=
5
# i/q-mult. per bit for 1 full issr run :
20
...
500 (10 loops: 50)
Table 6.1.
Computational complexity of the issr algorithm.
