Digital Signal Processing Reference
In-Depth Information
of the chip integration team, the digital section can revert to the last resort
and go underground: through substrate coupling and a finite common mode
rejection ratio (cmrr), switching noise will find its way to the most sensitive
nodes of analog signal path and decreases the sensitivity of the receiver. Several
techniques exist to shield the noisy digital circuits from the analog section: on-
chip decoupling of power supply lines or guard rings that pick up unwanted
substrate noise and lead it away to a stable ground connection. Also, the analog
circuits themselves can be hardened against external in-coupling noise by an
extensive use of differential signaling.
Other approaches go directly to the source of the problem by twiddling with
the frequency at which the digital part is clocked. This way spurious emis-
sions at some higher harmonic of the clock signal can be kept away from the
frequency band-of-interest. Sometimes, clock-dithering is also being used in
switching circuits to avoid single-tone spurious emissions. However, dithering
merely spreads the same amount of noise power over a larger chunk of the
radio spectrum and is thus of very little interest for wideband receivers. For
the pulse-based radio receiver, there is still another way to prevent noise from
leaking into the front-end of the system. The input of the receiver is most vul-
nerable to noise during the on-state of the receive window. For the remaining
time, the input stage is kept in some sort of low-impedance state where in-
terference and noise are blocked from entering the receiver. It is possible for
the digital section to suspend all non-critical activities during the active slot
of the main receive unit. This form of
radio silence
in the digital section will
temporarily boost the sensitivity of the receiver by a reduction of the noise
floor. Suspending the clock of a digital processor can be a dangerous operation
though, and should be taken into consideration early in the design process.
Stopping the clock leads to data loss in some processors. This is, for example,
the case in dynamic logic cmos systems [Cha00], where the voltage on iso-
lated floating nodes needs to be updated on a regular basis to counteract the
effects of charge leakage. Besides this, stopping and resuming the activity of
a large digital circuit causes a fluctuating current that is drawn from the power
supply. When this is accompanied by jumps in the supply voltage of the ana-
log section, the local oscillator (lo) of the receiver will suffer from unexpected
changes in the output phase. In a coherent receiver, a stable reference phase is
essential for the demodulation of the complex symbols. Of course, it is the task
of the xtal reference oscillator to suppress the phase noise of the voltage con-
trolled oscillator, but the reaction time of the phase-locked loop (pll) depends
on the reference frequency and the bandwidth of the loop. In order to allow the
lo-phase to stabilize, the digital clock should be muted slightly in advance of
the start of the next upcoming receive slot. When the rf-signal has been cap-
tured and the receive window is shut, the activities of the digital section can be
resumed.
