Digital Signal Processing Reference
In-Depth Information
5.4
System integration and clock planning
As a result of the very specific technical knowledge and the development costs
associated with in-house ic-design, end product vendors are shipping devices
that contain proprietary ip blocks from several different sources. In the never-
ending quest for cheaper and more reliable products, the vendors of ip com-
ponents try to offer off-the-shelf system-on-chip (SoC) implementations. In
many occasions, offering single-chip solutions is the only way to differentiate
themselves from their competitors. For wireless products this can be a major
challenge, since the analog circuits have to share the same die as the digital
signal processing circuits. For the inherently very sensitive analog circuits of a
wireless receiver this is a real performance killer, as their is possibly no better
way to get a broadband noise source any closer to the analog front-end.
There are several options for the digital section to annoy its analog neighbour to
death (illustrated in Figure 5.14). For a start, it can use the shared supply lines
to get the job done. If some smart designer would have taken this into account
and has avoided common power lines, the digital part will be smart enough to
deliberately make use of the antenna functionality of the bonding wires and get
the message delivered over the air. If this also fails due to a clever floorplanning
chip floorplanning
early in design process.
Use current-mode
logic for high-speed
digital (e.g. PLL).
inductive coupling
Use sufficient on-chip
decoupling capacitance.
Reduce voltage
swing of digital
output drivers.
supply-line coupling
I/O
ANALOG
DIGITAL
Mute non time-critical
digital operations
during receive state.
Frequency planning:
Avoid spurious signals
in the frequency band
of the analog section.
Use differential signaling
to reduce sensitivity to
in-coupling noise.
substrate coupling
Use low-impedance
ground and voltage
reference planes.
Route switching clock
lines perpendicular to
the sensitive signal path.
Guard rings lead
substrate noise to
nearby ground node.
Figure 5.14.
Ways to reduce noise injection into the analog section of a single-
chip receiver design with on-board signal processing. Injection of
digital noise in the front-end of the receiver reduces its sensitivity
to the weak antenna signals.
