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Bottom-up fabrication of
nanoscale elements onto units
2
3
Programming units
and interconnections
1
Photolithography patterning
microscale interconnected
units
Functional circuit
Figure 11.7. The meet-in-between paradigm based on programmable units of
nanoscale basic elements, such as molecules, nanowires, and carbon nanotubes.
For example, a unit can be a silicon nanowire crossbar array or a molecular
nanocell [79].
defect tolerance and a fabrication simplicity that is unrivaled by other molecular
electronic architectures.
A nanocell is a two-dimensional (three-dimensional models could also be
considered) network of self-assembled metallic particles connected by molecules
that show reprogrammable (can be turned ''on'' or ''off '') negative differential
resistance (NDR) or even other switching and/or memory properties. The
nanocell is surrounded by a small number of lithographically defined access leads
at the edges of the nanocell. Figure 11.8 shows an assembled nanocell. Unlike
typical chip fabrication, the nanocell is not constructed as a specific logic gate and
the internal topology is, for the most part, disordered. Logic is created in the
nanocell by training it post-fabrication, similar in some respects to a field-
programmable gate array (FPGA). Even if this process is only a few percent
efficient in the use molecular devices, very high logic densities will be possible.
Moreover, the nanocell has the potential to be reprogrammed throughout a
computational process via changes in the ''on'' and ''off '' states of the molecules,
thereby creating a real-time dynamic reconfigurable hard-wired logic. The CPU of
the computer would be comprised of arrays of nanocells wherein each nanocell
would have the functionality of many transistors working in concert. A regular
array of nanocells is assumed to manage complexity, and ultimately, a few
nanocells, once programmed, should be capable of programming their neighbor-
ing nanocells through bootstrapping heuristics. Alternatively, arrays could be
programmed one nanocell at a time via an underlying CMOS platform.
 
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