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and propagating reliability values in stages, exploiting the inherent structural
decomposition of the circuit. To demonstrate how this general scalable technique
can make the reliability evaluation methodologies more scalable, [69] develop an
algorithm specifically for the PMC-based methodology. Since the PTM and PGM
approaches are similar to the PMC approach, minor modifications to this
algorithm can also scale the PTM and PGM methodologies.
10.5. CONCLUSIONS
This chapter provides a very short and cursory glimpse of the different techniques
that are being used to mitigate the high percentage of defective devices per chip
produced by nanoscale fabrication or self-assembly processes. Many of these
techniques have high cost in terms of redundancy factor (the ratio of number of
devices needed to enforce tolerance in presence of defects and faults to the number
of devices needed to implement a logic in absence of faults/defects), area, and
power dissipation. An argument in support of using such expensive techniques has
often been that at the nanoscale, there will be an abundance of devices, many more
than needed for the functionality to be implemented. However, in some cases,
the cost is exponentially high, and hence cannot be paid in practice. As a result, the
reconfiguration techniques to avoid defects and faults seem to be more attractive
solutions, in light of the facts that self-assembled nanofabrics are likely to
be regular; with such large number of devices, it is likely that regular fabrics
will be the best substrate to create complex logics on, rather than the current
practice of random logical layouts on chips.
In any case, we hope that this chapter provides the reader with the preliminary
background needed to delve into further details on the various redundancy
techniques to mitigate defects and faults in the nanoscale computing. A large
body of literature exists on these techniques (pointers to some of which can
be found in the bibliographic references) but a lot of the important pointers can be
found within the articles referenced here. Similar comments apply to the extensive
literature on reconfigurable nanocomputing. The choice of references and topics
in this chapter does not indicate any valuation on our part as to which of these
articles constitute the most important contributions in this field, but are rather
based on our familiarity with the chosen topics and articles.
REFERENCES
1. International
technology roadmap for semiconductors, 2005. http://www.public.
itrs.net.
2. E. J. Nowak. Maintaining the benefits of CMOS scaling when scaling bogs down. IBM
Journal of Research and Development, 46(2-3): pp 169-180, 2002.
3. C. H. Bennett. The thermodynamics of computation-a review. International Journal of
Theoretical Physics, 21(905-940): 1982.
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