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4. M. Forshaw, R. Stadler, D. Crawley, and K. Nikolic. A short review of nanoelectronic
architectures, Nanotechnology, 15: pp S220-S223, 2004.
5. J. Meindl, Q. Chen, and J. Davis. Limits on silicon nanoelectronics for terascale
integration. Science, 293: pp 2044-2049, 2001.
6. S. Kim, C. H. Ziesler, and M. C. Papaefthymiou. Charge-recovery computing on
silicon, 54: pp 651-659, 2005.
7. R. Landauer. Uncertainty principle and minimal energy-dissipation in the computer,
International Journal of Theoretical Physics, 21: pp 283-297, 1982.
8. W. C. Athas, L. J. Swensson, J. G. Koller, and N. Tzartzanis. Low-power digital
systems based on adiabatic-switching principles, IEEE Transactions on VLSI Systems,
2: pp 398-407, 1994.
9. P. Beckett and A. Jennings. Towards nanocomputer architecture. In: ACS Conferences
in Research and Practice in Information Technology (CRPIT), ser. Computer Systems
Architecture, 6. Australian Computer Society, 2002. http://www.cellmatrix.com/entry-
way/ products/pub/publications.html.
10. A. Tannenbaum. Distributed Systems: Principles and Paradigms. Upper-Saddle River,
NJ: Prentice Hall, 2002.
11. P. Jalote. Fault Tolerance in Distributed Systems. Upper Saddle River, NJ: Prentice
Hall, 1994.
12. D. P. Siewiorek and R. S. Swarz. Reliable Computer Systems: Design and Evaluation,
2nd ed. Burlington, MA: Digital Press, 1992.
13. S. Habinc. Funtional triple modular redundancy (ftmr): Vhdl design methodology for
redundancy in combinatorial and sequential logic. NASA office of logic design,
Technical Report, 2002. http://klabs.org/richcontent/fpga_content/pages/notes/seu_
hardening.htm.
14. P. Graham and M. Gokhale. Nanocomputing in the presence of defects and faults:
A survey. In: Nano, Quantum and Molecular Computing: Implications to High Level
Design and Validation. Amsterdam: Kluwer, 2004, pp 39-72.
15. W. H. Pierce. Fault-Tolerant Computer Design. New York: Academic Press, 1965.
16. J. Han and P. Jonker. A defect- and fault-tolerant architecture for nanocomputers.
Nanotechnology, pp 224-230, 2003.
17. A. DeHon. Array-based architecture for fet-based nanoscale electronics. IEEE Trans-
actions on Nanotechnology, 2: pp 223-232, 2003.
18. A. DeHon and M. J. Wilson. Nanowire-based sublithographic programmable logic
arrays. In: International Symposium on FPGAs, 2004: pp 123-132.
19. S. C. Goldstein and M. Budiu. Nanofabrics: Spatial computing using molecular
electronics. In: Annual International Symposium on Computer Architecture (ISCA),
July 2001: pp 178-189.
20. J. Heath, P. Kuekes, G. Snider, and R. Williams. A defect tolerant computer
architecture: Opportunities for nanotechnology. Science, 80: pp 1716-1721, 1998.
21. M. Mishra and S. C. Goldstein. Defect tolerance at the end of the roadmap. In: Test
Conference (ITC), Charlotte, North Carolina, Sep 30-Oct 2, 2003.
22. J. Patwardhan, C. Dwyer, A. Lebeck, and D. Sorin. Evaluating the connectivity of self-
assembled networks of nano-scale processing elements. In: IEEE International Work-
shop on Design and Test of Defect-Tolerant Nanoscale Architectures, May 2005.
 
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