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Deflection layer
with microelectro
mechanical mirrors
Electro-optical
Interconnects
Microscale
processing
layer
Nanoscale
processing
layer
Figure
7.12.
The hierarchical multiscale architecture.
electrical interconnections, while the fixed mirrors provide vertical paths among
processors.
Since only electrical switches and fixed mirrors are used, this architecture has
a switching time of nanoseconds. In the example shown in Figure 7.12, the
electrical connection between P(4,1) and P(4,4) has been highlighted, and the
electro-optical routing from processor P(1,1) to processor P(3,3) is shown. P(1,1)
makes an electrical connection to P(1,3) while P(1,3) is connected to P(3,3) using
M(1,3) fixed mirror.
7.7. PRELIMINARY IMPLEMENTATIONS
While the architectures presented in the previous section have not yet been fully
implemented, we have some preliminary experimental results based on a simple
prototype that is built and tested by our collaborators. The significant point about
these experimental results is that the architectures are operable at room tempera-
ture and currently have GHz switching speed. In the following, we first show some
numerical simulations that illustrate the functionality of a simple logic device.
Next, our prototype and experimental results are presented, along with a
theoretical discussion explaining the operation of the prototype.
7.7.1. Spin-Wave-Based Logic Devices
Spin waves can be used to provide an ''LC'' coupling of devices, without
dissipative resistance. With the spin-wave concept, the spin rotates as a propagat-
ing wave and there is no particle (electron/hole) transport. In Figure 7.13 we have
schematically shown a prototype structure for spin-wave bus demonstration. The
core of the structure consists of a ferromagnetic film (NiFe, for example) grown on
a semi-insulating substrate. The film is polarized, along with the x axis. There
are three asymmetric co-planar strip (ACPS) transmission lines on the top of the
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