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technologies, which have a set input/output that provides a built-in directionality
for information flow, the clock also controls the direction of information flow in a
QCA circuit. In addition to this, the clock provides the power gain required for
proper circuit operation [54]. By clocking the cells quasi-adiabatically, proble-
matic metastable states can be minimized.
Clocking three-state QCA cells (six-dot cells) can be accomplished by
modulating the potential of the two central dots of the cell. This applied potential
modifies the potential energy of the NULL state. When the NULL state has the
lowest energy, the cell will tend to relax to this state. When the clock potential is
increased, the energy of the NULL state will be higher than that of the two
ACTIVE states and the cell will tend to the ACTIVE state with the lowest
potential energy, determined by the perturbation provided by neighboring cells.
A mechanism for clocking has also been proposed for a four-dot cell that
involves a controlled ability to raise and lower the quantum mechanical tunneling
barriers between the dots of the cell, thus forcing the cell into and out of a
quantum mechanical superposition of the two ACTIVE states. When the tunnel-
ing barriers are high, charges in the cell become localized in one particular
electronic configuration; as a result, the cell is said to be latched and the cell will
not switch regardless of the influence of neighboring cells. When the tunneling
barriers are low, the electronic wave function becomes delocalized (P=0) and the
cell is said to be in the NULL polarization state.
There are advantages to building QCA circuit design tools around this
particular approach to clocking because the Hamiltonian for each cell can be
reduced from three-states (3
3 matrix) to two-states (2
2 matrix). This
reduction significantly lowers the computational requirements for large circuits.
QCADesigner is designed around this model and is therefore capable of simulat-
ing fairly large circuits [46].
4.5.1. Zone Clocking
With zone clocking, all the cells in a design are grouped into one of four available
clocking zones; that is, all the cells in a particular clocking zone are connected to
one of the four available phases of the QCA clock, as shown in Figure 4.7 [55].
The successive latching and unlatching of cells connected to the different clock
phases acts to pump information throughout the circuit. For example, a wire,
which is clocked from left to right with increasing clocking zones, will propagate
information in the same direction. As a result, QCA circuits are pipelined at
the clocking zone level. This also permits more than one bit of information to be
present on a particular wire. QCADesigner has been developed around this
particular approach to clocking, and the example circuits presented in this chapter
are based on results using this method.
Within the zone clocking scheme, each group of cells connected to a particular
phase of the clock can be modeled as a D-latch [56]. As each group of cells in a
particular clocking zone becomes latched, they retain their information until the
clock is relaxed, independent of changes in the polarization of neighboring cells.
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