Hardware Reference
In-Depth Information
OE
CE
t
WP
t
WPH
t
BLC
WE
t
AS
t
AH
A0-A12
Valid addr.
t
DS
t
DH
Data
Valid data
Byte 0
Byte 126
Byte 127
Byte 1
Byte 2
Byte 3
t
WC
Figure 14.41
■
AT28C010 page-mode write waveform
Symbol
Parameter
Min
Max
Unit
t
WC
t
AS
t
AH
t
DS
t
DH
t
WP
t
BLC
t
WPH
Write cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Write pulse width
Byte load cycle time
Write pulse width high
10
ms
ns
ns
ns
ns
ns
μ
0
50
50
0
100
50
150
s
ns
Table 14.13
■
AT28CO10 page-write characteristics
half but may lower the system cost slightly. When adding 8-bit-wide external memory, the data
output of memory is connected to Port A.
This section illustrates how to add 256 kB of SRAM and 256 kB of EEPROM to the HCS12
by using the paging technique. The application program needs to go through the paging window
located from $8000 to $BFFF in order to access these two memory modules.
Because this design will be using two 128-kB SRAM chips (K6R1008C1D) to construct 256 kB
of 16-bit-wide memory, the lowest 13 address signals (A13, . . . , A1) and the expanded address sig-
nals XA14, . . . , XA17 will be used as address inputs for both SRAM chips. The A0 signal will not be
needed. Because these two chips must be selected by the same chip-select signal, the address space
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