Hardware Reference
In-Depth Information
must be divided into 256-kB blocks when making memory space assignment to the SRAM module.
The following assignment will be appropriate:
SRAM module:
$00000-$3FFFF
EEPROM module:
$40000-$7FFFF
14.10.2 Address Latch
Since the address signals A15, . . . , A0 and data signals D15, . . . , D0 are time multiplexed,
they need to be latched into a memory device such as the dual octal latch 74ABT16373B (made
by Philips) and held valid throughout the whole bus cycle. This device uses the falling edge of
its enable inputs (1E and 2E) to latch the data inputs. The ECS signal (or XCS for some devices)
of the HCS12 can be used to drive this input and latch the address signals A15, . . . , A0 into the
74ABT16373B. The pin assignment of the 74ABT16373B is shown in Figure 14.42.
The values of 1D0, . . . , 1D7 and 2D0, . . . , 2D7 are latched into 1Q0, . . . , 1Q7 and 2Q0, . . . ,
2Q7 on the falling edges of the 1E and 2E signals, respectively. The propagation delay from the fall-
ing edge of 1E (or 2E) to 1Q0, . . . , 1Q7 (or 2Q0, . . . , 2Q7) is 4.4 ns. The propagation delay from 1D x
( x 5 0, . . . ,7) to 1Q x is also 4.4 ns in the worst case. When the 1E (or 2E) signal is high, the latch is
transparent; that is, the value on 1D x (2D x ) will appear on 1Q x (2Q x ) after the propagation delay.
The required data setup and hold times for 1D x (and 2D x ) are 1 ns and 0.5 ns, respectively. The
outputs 1Q0, . . . , 1Q7 (2Q0, . . . , 2Q7) will be in high impedance if the 1OE (2OE) signal is high.
1OE
1Q0
1Q1
GND
1Q2
1Q3
V CC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
V CC
2Q4
2Q5
GND
2Q6
2Q7
2OE
1
48
1E
1D0
1D1
GND
1D2
1D3
V CC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V CC
2D4
2D5
GND
2D6
2D7
2E
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Figure 14.42 Pin assignment
of 74ABT16373B
 
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