Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
CBEIF
CCIF
PVIOL
ACCERR
0
BLANK
0
0
base+$115
Reset:
1
1
0
0
0
0
0
0
CBEIF: command buffer empty interrupt flag
0 = command buffers are full.
1 = command buffers are ready to accept a new command.
CCIF: command completion interrupt flag
0 = command in progress.
1 = all commands are completed.
PVIOL: protection violation
0 = no failure.
1 = a protection violation has occurred.
ACCERR: flash access error
0 = no failure.
1 = access error has occurred.
BLANK: array has been verified as erased
0 = if an erase and verify command has been requested, and the CCIF flag is set,
then a zero in BLANK indicates that the block is not erased.
1 = flash block verifies as erased.
Figure 14.22
■
EEPROM status register (ESTAT)
7
6
5
4
3
2
1
0
0
CMDB6
CMDB5
0
0
CMDB2
0
CMDB0
base+$116
Reset:
1
1
0
0
0
0
0
0
CMDB6, CMDB5, CMDB2, and CMDB0: command bits
Valid commands include the following:
$05 = erase and verify.
$20 = program a word (2 bytes).
$40 = sector erase.
$41 = bulk erase.
$60 = sector modify.
Figure 14.23
■
EEPROM command buffer and register (ECMD)
The timing for EEPROM programming and erasure is controlled by the ECLKDIV register.
The bit definitions and configuration are identical to those of the FCLKDIV register for the
flash memory. We need to write a value to divide the oscillator frequency down to a range from
150 to 200 kHz.
The algorithm for programming the EEPROM is illustrated in Figure 14.24. It is almost
identical to the algorithm for programming the flash memory.
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