Hardware Reference
In-Depth Information
protection for that block is fully disabled; that is, FOPEN 5 1, FPHDIS 5 1, and FPLDIS 5 1. The
contents of the FPROT register are loaded from 1 byte of four locations, $FF0A,$FF0D. This is
indicated by the letter F in Figure 14.9.
In addition to the FPROT registers, the following registers are related to the configuration
and operation control of the flash memory.
F
LASH
C
LOCK
D
IVIDER
R
EGISTER
(FLCKDIV)
This register is not banked and is used to control the timed events in programming and era-
sure algorithms. The contents of this register are shown in Figure 14.10. Bit 7 is read only; other
bits are readable and writable.
7
6
3
0
5
4
2
1
Reset value
= 0x00
FDIVLD
PRDIV8
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
Reset:
0
0
0
0
0
0
0
0
FDIVLD: clock divider loaded
0 = register has not been written.
1 = register has been written to since the last reset.
PRDIV8: enable prescaler by 8
0 = the input oscillator clock is directly fed into the FCLKDIV divider.
1 = enables a divide-by-8 prescaler, to divide the flash module input oscillator
clock before feeding into the CLKDIV divider.
FDIV[5:0]: clock divider bits
The combination of PRDIV8 and FDIV[5:0] effectively divides the flash module
input oscillator clock down to a frequency of 150 kHz
,
200 kHz. The maximum
divide ratio is 512.
Figure 14.10
■
Flash clock divider register (FCLKDIV)
In order to guarantee that the on-chip flash memory and EEPROM can be programmed and
erased properly, the clock signal that controls the timing of programming and erasure should be
configured properly. The only clock configuration to be done is to set the prescaler of the clock
by programming this register. The startup routine of the HCS12 needs to check the FDIVLD bit
to make sure that the prescaler has been configured. Depending on the oscillator frequency, the
designer may choose to insert or bypass a divide-by-8 prescaler to the clock signal for control-
ling the programming and erasure of the flash memory and EEPROM. The procedure for config-
uring the clock prescaler is discussed in Section 14.5.6.
F
LASH
S
ECURITY
R
EGISTER
(FSEC)
This register holds all the bits associated with the device security. The contents of this
register are shown in Figure 14.11. All the bits of this register are readable but not writ-
able. This register is loaded from the flash protection/options field byte at $FF0F during
the reset sequence, indicated by F in Figure 14.11. This register is not banked. The SEC1
and SEC0 bits define the security state of the device. If the flash is unsecured using the
Backdoor Key Access, the SEC bits are forced to 10. The HCS12 security function is dis-
cussed in Section 14.5.4.
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