Controller Area Network (CAN) - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 652

7 6 5 4 3 2 1 0

SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

Reset: 0 0 0 0 0 0 0 0

SJW1, SJW0: synchronization jump width
00 = 1 t Q clock cycle.
01 = 2 t Q clock cycle.

10 = 3 t Q clock cycle.
11 = 4

t Q clock cycle.
BRP5 , BRP0: baud rate prescaler
000000 = 1.
000001 = 2.
000010 = 3.
111110 = 63.
111111 = 64.

Figure 13.19 ■ MSCAN control register 0 (CAN x BTRO, x 5 0, 1, 2, 3, or 4)

MSCAN B US T IMING R EGISTER 1 (CAN X BTR1)
This register provides for control on phase_seg1 and phase_seg2 in Figure 13.12. The con-
tents of the CAN x BTR1 register are shown in Figure 13.20. When three samples are taken, the
bit value is determined by the majority function of these samples. Two adjacent samples are
separated by one time quantum.

7 6 5 4 3 2 1 0

Reset value
= 0x00

SAMP

TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10

SAMP: sampling
0 = one sample per bit.
1 = three samples per bit.
TSEG22 , TSEG20: time segment 2
000 = 1 t Q clock cycle.
001 = 2 t Q clock cycles.
110 = 7 t Q clock cycles.

111 = 8 t Q clock cycles.

TSEG13 , TSEG10: time segment 1
0000 = 1 t Q clock cycle.

0001 = 2 t Q clock cycles.

1110 = 15 t Q clock cycles.
1111 = 16

t Q clock cycles.
Figure 13.20 ■ MSCAN control register 1 (CAN x BTR1, x 5 0, 1, 2, 3, or 4)