Hardware Reference
In-Depth Information
11.6.2 RTC and RAM Address Map
The address map for the RTC and RAM registers of the DS1307 is shown in Figure 11.28.
The RTC registers are located at address locations $00 to $07. The RAM registers are located at
address locations $08 to $3F. During a multibyte access, when the address pointer reaches $3F,
it wraps around to location $00, the beginning of the clock space.
Seconds
$00
$01
Minutes
$02
Hours
$03
Day
$04
Date
$05
Month
$06
Year
$07
$08
Control
RAM
56 × 8
$3F
Figure 11.28 DS1307 address map
11.6.3 Clock and Calendar
The time and calendar information is obtained by reading the appropriate register bytes.
The contents of the RTC registers are illustrated in Figure 11.29. The time and calendar are set
or initialized by writing the appropriate register bytes, and the contents of the registers are in
the BCD format. Bit 7 of register 0 is the clock halt (CH) bit. When this bit is set to 1, the oscil-
lator is disabled. When this bit is a 0, the oscillator is enabled. This bit should be cleared to 0
after reset. The initial power-on states of all registers are not defined. It is important that the
designer remembers to enable the oscillator during the initial configuration.
The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is
defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the
12-hour mode, bit 5 is the AM/PM bit, with logic high being PM. In the 24-hour mode, bit 5 is
the second 10-hour bit (20,23 hours).
11.6.4 The DS1307 Control Register
The contents of the control register are shown in the bottom row of Figure 11.29. Bit 7 con-
trols the output level of the SQWOUT pin when the square output is disabled (i.e., the SQWE
bit is 0). When bit 7 is 1, the SQWOUT output level is 1 when bit 4 (the SQWE bit) is set to 0.
Otherwise, the SQWOUT output level is 0. The SQWE bit enables the SQWOUT pin (oscilla-
tor) output. The frequency of the SQWOUT output depends on the values of the RS1,RS0 bits.
With the square wave output set to 1 Hz, the clock registers are updated on the falling edge of
the square wave.
 
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