Hardware Reference
In-Depth Information
The same operation can be performed by the following C statements:
IBCR &
5
,
TXRX;
/* prepare to receive */
IBCR |
5
TXAK;
/* prepare not to acknowledge */
dummy
5
IBDR;
/* a dummy read to trigger nine clock pulses */
while(!(IBSR & IBIF));
/* wait for a byte to shift in */
IBSR
5
IBIF;
/* clear the IBIF flag */
IBCR &
5
,
MSSL;
/* generate a stop condition */
buf
5
IBDR;
/* place the received byte in
buf
*/
In slave mode, the I
2
C module cannot initiate any data transfer. After reset and a stop con-
dition, the I
2
C module is in slave mode. Once the I
2
C module is enabled in slave mode, it waits
for a start condition to occur. Following the start condition, 8 bits are shifted into the IBDR
register. The value of the upper 7 bits of the received byte is compared with the IBAD register. If
the address matches, the following events occur:
•
The bit 0 of the address byte is copied into the SRW bit of the IBSR register.
•
The IAAS bit is set to indicate address match.
•
An ACK pulse is generated regardless of the value of the TxAK bit.
•
The IBIF flag is set.
After the address match, the I
2
C module in slave mode should acknowledge every data byte
received.
When operating in slave mode, the user program needs to make sure that the address match
has occurred before it prepares to receive or transmit. The following instruction sequence can
detect the address match and take appropriate actions:
brset IBSR,IAAS,addr_match
; is address matched?
…
addr_match
brclr
IBSR,SRW,slave_rd
bset
IBCR,TXRX
; prepare to transmit data
movb tx_buf,IBDR
; place data in IBDR to wait for SCL to shift it out
brclr
IBSR,IBIF,*
; wait for data to be shifted out
…
slave_rd
bclr
IBCR,TXAK
1
TXRX
; prepare to receive and send ACK
brclr
IBSR,IBIF,*
; wait for data byte to shift in
movb #IBIF,IBSR
; clear the IBIF flag
movb IBDR,rcv_buf
; save the received data
…
Data transmission and reception in I
2
C protocol can also be made interrupt-driven. Using the
interrupt mechanism to control data transmission and reception allows the MCU to perform
other tasks during the waiting period.
The DS1307 is a real-time clock (RTC) chip that uses BCD format to represent clock and
calendar information. It has 56 bytes of nonvolatile SRAM for storing critical information. The
address and data are transferred via the I
2
C bus. The clock and calendar provide seconds, min-
utes, hours, day, date, month, and year information. The end-of-the-month data is automatically
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