Inter-Integrated Circuit (I2C) Interface - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 551

The following C statements send out the variable cx via the I 2 C bus:
IBDR 5 cx; /* send out the value cx */
while (!(IBSR & IBIF)); /* wait until the byte is shifted out */
IBSR 5 IBIF; /* clear the IBIF flag */
To send multiple bytes to the slave, one can place the previous three instructions in a loop and
use an index register to point to the data to be sent. The loop will be executed as many times as
needed to send out all the data bytes.
After sending out the slave ID and receiving the acknowledgement from the slave, the I 2 C
module can read a data byte by performing the following steps:
Step 1
Clear the Tx/Rx bit of the IBCR register to 0 for data reception. Clear the TxAK bit of the
IBCR register to 0 if the user wants to acknowledge the data byte. This should be done
when the user wants to receive multiple bytes from the same slave. If the user wants to
read only 1 byte or when the byte to be read is the last byte of a read sequence, then the
TxAK bit should be set to 1. Without receiving acknowledgement, the slave will stop
driving the SDA line at the end of the eight clock pulses.
Step 2
Perform a dummy read. This action will trigger nine clock pulses to be sent out on the
SCL pin to shift in 8 data bits and send out acknowledgement.
Step 3
Wait until the IBIF flag is set to 1.
Step 4
Clear the IBIF flag by writing a 1 to it.
The following instruction sequence reads a byte and acknowledges it:
bclr IBCR,TXRX 1 TXAK ; prepare to receive and acknowledge
ldaa IBDR ; a dummy read to trigger nine clock pulses
brclr IBSR,IBIF,* ; wait until the data byte is shifted in
movb #IBIF,IBSR ; clear the IBIF flag
ldaa IBDR ; place the received byte in A and also initiate the
; next read sequence
The same read operation can be performed by the following C statements:
IBCR & 5 , (TXRX 1 TXAK); /* prepare to receive and acknowledge */
dummy 5 IBDR; /* a dummy read */
while(!(IBSR & IBIF)); /* wait for the byte to shift in */
IBSR 5 IBIF; /* clear the IBIF flag */
buf 5 IBDR; /* place the received byte in buf and also initiate
the next read sequence */
The following instruction sequence reads a byte, sends out a negative acknowledgement, and
also generates a stop condition:

bclr IBCR,TXRX ; prepare to receive

bset IBCR,TXAK ; to send negative acknowledgement

ldaa IBDR ; dummy read to trigger clock pulses

brclr IBSR,IBIF,* ; wait until the byte is shifted in

movb #IBIF,IBSR ; clear the IBIF flag

bclr IBCR,MSSL ; generate a stop condition

ldaa IBDR ; place the received byte in A