Inter-Integrated Circuit (I2C) Interface - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 549

The computed values satisfy the requirements. A quicker way of timing verifi cation is to use
the numbers listed in Table 11.6 instead of using Equations 11.2 to 11.4.

▲

11.5 Programming the I 2 C Module

Before the I 2 C module can transmit and receive data correctly, it must be initialized prop-
erly. The initialization procedure is as follows:
• Compute the value that can obtain the SCL frequency from the E-clock and use it
to update the IBFD register.
• Optionally load the IBAD register to define its slave address.
• Set the IBEN bit of the IBCR register to enable the I 2 C system.
• Modify the bits of the IBCR register to select master/slave mode, transmit/receive
mode, and interrupt enable mode
The initialization of the I 2 C module can be performed using a macro or a subroutine. The sub-
routine that performs the I 2 C initialization is as follows:
; ************************* ************************* *******************
; The following function has two incoming parameters passed in accumulators A and B
; to set up baud rate and slave address, respectively.
; ************************* ************************* *******************
openI2C bset IBCR,IBEN ; enable I 2 C module

staa IBFD ; establish SCL frequency

stab IBAD ; establish I 2 C module slave address

bclr IBCR,IBIE ; disable I 2 C interrupt

bset IBCR,IBSWAI ; disable I 2 C in wait mode

rts
The C language version of the subroutine is as follows:
void openI2C(char ibc, char i2c_ID)
{

IBCR | 5 IBEN; /* enable I 2 C module */

IBFD 5 ibc; /* set up I2C baud rate */

IBAD 5 i2c_ID; /* set up slave address */

IBCR & 5 , IBIE; /* disable I 2 C interrupt */

IBCR | 5 IBSWAI; /* disable I 2 C in wait mode */

}
A successful data exchange on the I 2 C bus requires the user to generate the I 2 C signal com-
ponents in a proper order. The generation of these signal components is described in the follow-
ing sections.

11.5.1 Generation of the Start Condition
All data transmissions in the I 2 C bus begin with the start condition. The start condition can
only be sent when the bus is idle. If the MCU is connected to a multimaster bus system, the
state of the IBB bit of the IBSR register must be tested to check whether the serial bus is busy.
If the bus is idle (IBB 5 0), the sta rt condition and the first byte can be sent. The first byte
consists of the slave address and the R/W bit. The bus free time (i.e., the time between a stop con-
dition and the following start condition) is built into the hardware that generates the start cycle.