Inter-Integrated Circuit (I2C) Interface - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 548

Example 11.1
▼ Assuming that the HCS12 is running with a 24-MHz bus clock, compute the values to be
written into the IBFD register to set the baud rate to 100 and 400 kHz.
Solution
Case 1: Baud rate 5 100 kHz
SCL divider 5 24 MHz 4 100 kHz 5 240

From Table 11.6, there is only one IBFD value ($1F) associated with this SCL divider value. Us-
ing this value to look up Tables 11.3, 11.4, and 11.5, we obtain the following parameter values:
• MUL 5 1
• scl2tap 5 6
• tap2tap 5 8
• scl2start 5 6
• scl2stop 5 9
• SDA_tap 5 4
• SCL_tap 5 15
SDA hold time 5 MUL 3 {scl2tap 1 [(SDA_tap 2 1) 3 tap2tap] 1 3)}
5 1 3 {6 1 [(4 2 1) 3 8] 1 3)}
5 33 E cycles 5 1.375 μ s ( , 3.45 μ s)
SCL hold time (start) 5 MUL 3 [scl2start 1 (SCL_tap 2 1) 3 tap2tap]
5 1 3 [6 1 (15 2 1) 3 8] 5 118 E cycles 5 4.92 μ s ( . 4.0 μ s)
SCL hold time (stop) 5 MUL 3 [scl2stop 1 (SCL_tap 2 1) 3 tap2tap]
5 1 3 [9 1 (15 2 1) 3 8] 5 121 E cycles 5 5.04 μ s ( . 4.0 μ s)
The computed values satisfy the requirements.

Case 2: Baud rate 5 400 kHz
SCL divider 5 24 MHz 4 400 kHz 5 60

From Table 11.6, there is only one corresponding IBFD value ($45) for this SCL divider value. Us-
ing this value to look up Tables 11.3, 11.4, and 11.5, we obtain the following parameter values:
• MUL 5 2
• scl2tap 5 4
• tap2tap 5 1
• scl2start 5 2
• scl2stop 5 7
• SDA_tap 5 3
• SCL_tap 5 10
SDA hold time 5 2 3 {scl2tap 1 [(SDA_tap 2 1) 3 tap2tap] 1 3)}

5 2 3 {4 1 [(3 2 1) 3 1 ] 1 3}

5 18 E cycles 5 0.75 μ s ( , 0.9 μ s)

SCL hold time (start) 5 MUL 3 [scl2start 1 (SCL_tap 2 1) 3 tap2tap]

5 2 3 [2 1 (10 2 1) 3 1] 5 22 E cycles 5 0.917 μ s ( . 0.6 μ s)

SCL hold time (stop) 5 MUL 3 [scl2stop 1 (SCL_tap 2 1) 3 tap2tap]

5 2 3 [7 1 (10 2 1) 3 1] 5 32 E cycles 5 1.33 μ s ( . 0.6 μ s)