Hardware Reference
In-Depth Information
The inter-integrated circuit (I
2
C) serial interface protocol was developed by Philips in the
late 1980s. Version 1.0 was published in 1992. This version supports
•
Both the 100 kbps (
standard mode
)
and the 400 kbps (
fast mode
)
data rate
•
7-bit and 10-bit addressing
•
Slope control to improve electromagnetic compatibility (EMC) behavior
After the publication of version 1.0, I
2
C was well received by the embedded application
developers.
By 1998, the I
2
C protocol had become an industry standard; it has been licensed to more
than 50 companies and implemented in over 1000 different integrated circuits. However, many
applications require a higher data rate than that provided by the I
2
C protocol. Version 2.0 incor-
porates the
high-speed mode
(with a data rate of 3.4 Mbps) to address this requirement. Since
the I
2
C module of the HCS12 does not support the high-speed mode, it will not be discussed in
this chapter.
The I
2
C protocol has the following characteristics:
•
Synchronous in nature
. A data transfer is always initiated by a master device. A
clock signal (SCL) synchronizes the data transfer. The clock rate can vary without
disrupting the data. The data rate will simply change along with the changes in the
clock rate.
•
Master/slave model
. The master device controls the clock line (SCL). This line
dictates the timing of all data transfers on the I
2
C bus. Other devices can manipulate
this line, but they can only force the line low. By forcing the line low, it is possible to
clock more data into any device. This is known as clock stretching.
•
Bidirectional data transfer.
Data can flow in any direction on the I
2
C bus.
•
Serial interface method
.
I
2
C uses only signals SCL and SDA. The SCL signal is
the serial clock signal; the SDA signal is known as serial data. In reality, the SDA
signal can carry both the address and data.
I
2
C can have only two possible electrical states:
float high
and
driven low
. A master or
a slave device drives the I
2
C bus using an open-drain (or open-collector) driver. As shown in
Figure 11.1, both the SDA and SCL lines are pulled up to V
DD
via pull-up resistors. Because the
driver circuit is open drain, it can pull the I
2
C bus only to low. When the clock or data output
is low, the NMOS transistor is turned off. In this situation, no current flows from (to) the bus
to (from) the NMOS transistor, and hence the bus line will be pulled to high by the pull-up
resistor. Otherwise, the NMOS transistor is turned on and pulls the bus line to low.
The designer is free to use any resistor value for various speeds. But the calculation of what
value to use depends on the capacitance of the driven line and the speed of the I
2
C communica-
tion. In general, the recommended values for the pull-up resistors are 2.2 and 1 k
for standard
mode and fast mode, respectively. These values are found to work frequently. When the data
rate is below 100 kbps, the pull-up resistor should be set to 4.7 k
Ω
Ω
.
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