Introduction to the HCS12 Microcontroller - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 26

Branch offset is often specified using a label rather than a numeric value due to the difficulty
of calculating the exact value of the offset. For example, in the following instruction segment:
minus .
. ; if N (of CCR) 5 1
. ; PC ← PC 1 branch offset
bmi minus ; else
… ; PC ← PC
The instruction bmi minus causes the HCS12 to execute the instruction with the label
minus if the N flag of the CCR register is set to 1.
The assembler will calculate the appropriate branch offset when the symbol that represents
the branch target is encountered. Using a symbol to specify the branch target makes the pro-
gramming task easier and the resultant program more readable.
1.9.6 Indexed Addressing Modes
The indexed addressing mode uses two components to compute the effective address of
an operand or the target of a jump instruction. The first component is called the base address,
which is stored in a base register. The base register can be X, Y, SP, or PC. The second compo-
nent is called the offset, which is the distance of the target from the base address. The effective
address of the operand or jump target is the sum of these two components.
The offset may be a constant (5 bits, 9 bits, or 16 bits) or the contents of accumulator A, B,
or D. The base register may be pre- or postincremented or pre- or postdecremented. The size of
increment or decrement may be specified by the user and can be from 28 to 18. In addition, the
HCS12 also provides the user one level of indirection. That is, the sum of the contents of the
base register and the offset does not point to the actual operand or the jump target. Instead, it
points to the memory location that holds the address of the actual operand or jump target.
The variations of the indexed addressing mode are described in the following subsections.
1.9.7 Indexed Addressing Modes with Constant Offsets
The syntax of the indexed addressing mode with constant offset is as follows:
n , r
where
n is a 5-bit, 9-bit, or 16-bit constant
r is the base register and can be X, Y, SP, or PC
For example,
ldaa 4,X ; A ← [4 1 [X]]
loads the contents of the memory location with the address equal to the sum and 4 and X into A.
The HCS12 performs the following two operations for the ldd 100,Y instruction:
A ← [100 1 [Y]];
B ← [101 1 [Y]];
1.9.8 Indexed Addressing Mode with Offset in an Accumulator
The syntax of this form of indexed address mode is as follows:
acc, r
where
acc can be A, B, or D
r is the base register and can be X, Y, SP, or PC