Hardware Reference
In-Depth Information
The serial peripheral interface (SPI) allows the HCS12 to communicate synchronously with
peripheral devices and other microcontrollers. The SPI system in the HCS12 can operate as a
master or as a slave. When the SPI module is configured as a master, it is responsible for gen-
erating the clock signal (SCK) during an SPI data transfer. The SPI subsystem is mainly used
in interfacing with peripherals such as TTL shift registers, LED/LCD display drivers, phase-
locked-loop (PLL) chips, memory components with serial interface, or A/D and D/A converter
chips that do not need a very high data rate.
The SPI must be enabled to operate. When the SPI module is enabled, the four associated
SPI port pins are dedicated to the SPI function as
•
Slave select (SS)
•
Serial clock (SCK)
•
Master out/slave in (MOSI)
•
Master in/slave out (MISO)
The main element of the SPI system is the SPI data register. The 8-bit data register in the
master and the 8-bit data register in the slave are linked by the MOSI and the MISO pins to
form a distributed 16-bit register. When a data transfer is performed, this 16-bit register is seri-
ally shifted 8 bit positions by the SCK clock from the master; data is exchanged between the
master and the slave. Data written to the master SPI data register becomes the output data for
the slave, and data read from the master SPI data register after a transfer operation is the input
data from the slave.
A write to the SPI data register puts data into the transmit buffer if the previous transmis-
sion was complete. When a transfer is complete, received data is moved into a receiver data
register. Data may be read from this double-buffered system any time before the next transfer is
completed. This 8-bit register acts as the SPI receive data register for reads and as the SPI trans-
mit data register for writes. A single SPI register address is used for reading data from the read
data buffer and for writing data to the shifter.
There are four possible clock formats to choose from. The user selects one of these four
clock formats for data transfer by programming the CPOL and CPHA bits of the SPI control reg-
ister 1. The CPOL bit simply selects a noninverted (idle low) or inverted (idle high) clock. The
CPHA bit is used to accommodate two fundamentally different protocols by shifting the clock
a half-cycle or by not shifting the clock.
The SPI function on the HCS12 has been modified slightly from that in the 68HC11 with
the expectation of improving its applicability. An HCS12 device may have from one to three
identical SPI modules (SPI0, SPI1, and SPI2).
The SPI0 function shares the use of the upper four Port S pins: MISO0 (PS4), MOSI0 (PS5),
SCK0 (PS6), and SS0 (PS7). Out of reset, the SPI1 and SPI2 share the use of the lower four Port
P pins and upper four Port P pins, respectively. However, the SPI1 and SPI2 pins can also be
rerouted to the lower four Port H pins and upper four Port H pins by programming the MODRR
register. The assignment of SPI1 and SPI2 signal pins is described in Section 7.5.6. There is no
need to configure the pin directions when the SPI function is enabled.
•
MISO
x
(
x
5 0, 1, or 2):
master in slave out
(serial data input). This pin is used to
transmit data out of the SPI module when it is configured as a slave and receive
data when it is configured as a master.
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