The SPI Function - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 475

• MOSI x ( x 5 0, 1, or 2): master out slave in (serial data output). This pin is used to
transmit data out of the SPI module when it is configured as a master and receive
data when it is configured as a slave.
• SCK x ( x 5 0, 1, or 2): serial clock . This pin is used to carry the clock signal that
synchronizes SPI data transfer. It is an output if the SPI is configured as a master
but an input if the SPI is configured as a slave.
• SS x ( x 5 0, 1, or 2): slave select . When configured as a slave, this pin must be pulled
low for the SPI module to operate.

10.3 Registers Related to the SPI Subsystem

Most of the SPI operational parameters are set by two SPI control registers: SPI x CR1 ( x 5 0,
1, or 2) and SPI x CR2 ( x 5 0, 1, or 2). Their contents are shown in Figures 10.1 and 10.2, respec-
tively. The SPI must be enabled before it can start data transfer. Setting bit 6 of the SPI x CR1
register will enable the SPI subsystem. Bit 1 (SSOE) of the SPI x CR1 register allows the user to
use the SS pin to select the slave device for data transfer automatically. However, this feature is
not useful if the user wants to use the SPI to interface with multiple slave devices at the same
time. The selection of SS for input and output is shown in Table 10.1. Some slave devices may

7 6 5 4 3 2 1 0

Reset value
= 0x04

SPIE SPTIE MSTR CPOL CPHA SSOE LSBFE

SPE

SPIE: SPI interrupt enable bit
0 = SPI interrupts are disabled.
1 = SPI interrupts are enabled.
SPE: SPI system enable bit
0 = SPI disabled.
1 = SPI enabled and pins PS4-PS7 are dedicated to SPI function.
SPTIE: SPI transmit interrupt enable
0 = SPTEF interrupt disabled.
1 = SPTEF interrupt enabled.
MSTR: SPI master/slave mode select bit
0 = slave mode.
1 = master mode.
CPOL: SPI clock polarity bit
0 = active high clocks selected; SCK idle low.
1 = active low clocks selected; SCK idle high.
CPHA: SPI clock phase bit
0 = The first SCK edge is issued one-half cycle into the 8-cycle transfer operation.
1 = The SCK edge is issued at the beginning of the 8-cycle transfer operation.
SSOE: sla ve select output enable bit
The SS output feature is enabled only in master mode by asserting the
SSOE bit and the MODFEN bit of the SPIxCR2 register.
LSBF: SPI least significant bit first enable bit

0 = data is transferred most significant bit first.

1 = data is transferred least significant bit first.

Figure 10.1 ■ SPI control register 1 (SPI x CR1, x 5 0, 1, or 2)