Serial Communication Interface (SCI) - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 454

SCI data register

Idle
IRQ
RDRF/OR
IRQ

Interrupt
generation

RxD

Receive shift register

Receive and wake-up control

O
R
I
N
G

IRQ
to CPU

E-
clock

16 Data format control

Transmit control

TDRE
IRQ

Interrupt
generation

Transmit shift register

TC
IRQ

SCI data register

TxD

Figure 9.7 ■ HCS12SCI block diagram

The operation of an SCI module involves the following registers:
• Two baud rate registers . SCI x BDH and SCI x BDL ( x 5 0 or 1)
• Two control registers. SCI x CR1 and SCI x CR2 ( x 5 0 or 1)
• Two status registers . SCI x SR1 and SCI x SR2 ( x 5 0 or 1)
• Two data registers. SCI x DRH and SCI x DRL ( x 5 0 or 1)
The HCS12 SCI interface uses a data format of 1 start bit, 8 or 9 data bits, and 1 stop
bit. When the SCI is configured to use 9 data bits, one of the bits can be used as the parity
bit. The collection of the start bit, data bits, and the stop bit is called a frame. The SCI func-
tion has the capability to send a break to attract the attention of the other party of the data
communication. The SCI function supports hardware parity for transmission and reception.
When enabled, a parity bit is generated in hardware for transmitted data and received data. Re-
ceived parity errors are flagged in hardware. The SCI module supports two wake-up methods,
idle line wake-up and address mark wake-up; this allows the HCS12 to operate in a multiple-
node environment.

9.5 SCI Baud Rate Generation

The HCS12 SCI modules use a clock signal that is 16 times the data rate to detect the arrival
of the start bit and determine the logic value of data bits. The HCS12 SCI modules use a 13-bit
counter to generate this clock signal. This circuit is called a baud rate generator . To set the baud
rate to a certain value, one needs to write an appropriate value to the SCI x BDH:SCI x BDL register