Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
0
0
0
SBR12
SBR11
SBR10
SBR9
SBR8
Reset:
0
0
0
0
0
0
0
0
(a) SCI baud rate control register high (SCI0BDH/SCI1BDH)
7
6
5
4
3
2
1
0
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0
0
0
0
0
1
0
0
Reset:
(b) SCI baud rate control register low (SCI0BDL/SCI1BDL)
Figure 9.8
■
SCI baud rate control register
pair. The upper 3 bits of the SCI
x
BDH register are tied to zeros. The contents of these two regis-
ters are shown in Figure 9.8.
This baud rate generator divides down the E-clock to derive the clock signal for reception
and transmission. The value (referred to as
SBR
) to be written into the SCI
x
BDH:SCI
x
BDL reg-
ister pair can be derived by rounding the following expression to an integer value:
SBR
5
f
E
4
16
4
baud rate
The divide factors for the baud rate generator for the 16-MHz and 24-MHz E clocks are
listed in Table 9.3.
Baud Rate Divisor for
f
E
= 16 MHz
Baud Rate Divisor for
f
E
= 24 MHz
Desired SCI
Baud Rate
300
600
1200
2400
4800
9600
14,400
19,200
38,400
3333
1667
833
417
208
104
69
52
26
5000
2500
1250
625
313
156
104
78
39
Table 9.3
■
Baud rate generation
The operation of the SCI module is controlled by two control registers: SCI0CR1 (SCI1CR1)
and SCI0CR2 (SCI1CR2). Their contents are shown in Figures 9.9 and 9.10, respectively. The
SCI module allows full duplex, asynchronous, non-return-to-zero (NRZ) serial communication
between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver
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