Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 414

7 6 5 4 3 2 1 0

Reset value
= 0x00

0 0 0 0 0 0 DLY1 DLY0

DLYx: delay counter select bits
0 0 − disabled (bypassed)
0 1 − 256 P clock cycles (P clock has the same period as E-clock)
1 0 − 512 P clock cycles
1 1 − 1024 P clock cycles

Figure 8.37 ■ Delay Counter Control register (DLYCT)

input signal, after the preset delay, is the opposite of the level before the transition. This avoids
reaction to narrow pulses caused by noise. After counting, the counter is cleared automatically.

Example 8.19
▼ Modify the program in Example 8.2 to take advantage of the queue mode of the enhanced
input-capture function.
Solution: The modified program is as follows:
#include “c:\miniide\hcs12.inc”

org $1000

period ds.w 1 ; memory to store the period

org $1500

start movb #$90,TSCR ; enable timer counter and fast timer flag clear

bclr TIOS,IOS0 ; select input-capture 0

movb #$04,TSCR2 ; disable TCNT overflow interrupt, set prescale

; factor to 16

movb #$01,TCTL4 ; choose to capture the rising edge of PT0 pin

movb #$0A,ICSYS ; enable timer flag-setting mode, IC buffer, and queue

; mode

clr DLYCT ; disable delay counter

bset ICOVW,NOVW0 ; no input-capture overwrite for IC0

ldd TC0 ; empty the input-capture register TC0

ldd TC0H ; empty the holding register TC0H

brclr TFLG1,$FE,* ; wait for the arrival of the second rising edge

ldd TC0

subd TC0H ; subtract the first edge from the second edge

std period

swi
end
The C language version of the program is as follows:
#include “c:\cwHCS12\include\hcs12.h”
void main(void)
{

unsigned int period;

TSCR1 5 0x90; /* enable timer counter, enable fast timer flag clear*/

TIOS & 5 , IOS0; /* enable input-capture 0 */