Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 408

7 6 5 4 3 2 1 0

MCZI MODMC RDMCL ICLAT FLMC MCEN MCPR1 MCPR0

Reset: 0 0 0 0 0 0 0 0

MCZI: modulus counter underflow interrupt enable bit
0 = modulus counter underflow interrupt is disabled.
1 = modulus counter underflow interrupt is enabled.
MODMC: modulus mode enable bit
0 = the counter counts once from the value written to it and will stop at $0000.
1 = modulus mode is enabled. When the counter reaches $0000, the counter is
loaded with the latest value written into to the modulus count register.
RDMCL: read modulus down counter load bit
0 = reads of the modulus count register will return the present value of the count
register.
1 = reads of the modulus count register will return the contents of the load
register (i.e., the reload value is returned).
ICLAT: input-capture force latch action bit
This bit has effect only when both the LATQ and BUFEN bits in ICSYS are set.
0 = no effect.
1 = forces the contents of the input-capture registers TC0 to TC3 and their corres-
ponding 8-bit pulse accumulators to be latched into the associated holding registers.
The pulse accumulators will be cleared when the latch action occurs.
FLMC: force load register into the modulus counter count register bit
This bit has effect only when MCEN = 1.
0 = no effect.
1 = loads the load register into the modulus counter count register. This also resets
the modulus counter prescaler.
MCEN: modulus down counter enable bit
0 = modulus counter is disabled and preset to $FFFF.
1 = modulus counter is enabled.
MCPR1 and MCPR0: modulus counter prescaler select bits
0 0 = prescale rate is 1.
0 1 = prescale rate is 4.
1 0 = prescale rate is 8.
1 1 = prescale rate is 16.

Figure 8.32 ■ Modulus Down Counter register (MCCTL)

7 6 5 4 3 2 1 0

MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0

Reset: 0 0 0 0 0 0 0 0

MCZF: modulus counter underflow interrupt flag
This flag is set when the modulus down counter reaches 0. Writing
1 to this bit clears the flag.
POLF3:POLF0: first input-capture polarity status bits
These are read-only bits. Writing to these bits has no effect. Each
status bit gives the polarity of the first edge that has caused an input-
capture to occur after capture latch has been read.
0 = the first input-capture has been caused by a falling edge.
1 = the first input-capture has been caused by a rising edge.

Figure 8.33 ■ Modulus Down Counter Flag register (MCFLG)