Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 407

while(!(PAFLG & PAIF)); // wait for the arrival of the PAI falling edge

PACTL 5 0x00; // disable PA system

asm(“sei”);

pw 5 (long)paovCnt * 65536l 1 (long)PACNT;

asm (“swi”);

}
interrupt void paovISR (void)
{

PAFLG 5 PAOVF; // clear PAOVF flag

paovCnt 5 paovCnt 1 1;

}
The function for setting up an interrupt vector for the pulse accumulator A is identical to
that of Example 8.14.

▲

Example 8.16
▼ Write an instruction sequence to enable the 8-bit pulse accumulators PAC1 and PAC3
and let them increase on the rising edge of their associated pins. Disable their overflow
interrupts.
Solution: To enable PAC1 and PAC3, the PAEN and PBEN bits must be cleared and the
PA3EN and PA1EN bits set. To select the rising edge as their active edge, the value $44 needs
to be written into the TCTL4 register and also the PT3 and PT1 pins must be configured for
input-capture. To disable overflow interrupt, clear the PAOVI and PBOVI bits.
The following instruction sequence will perform the required configuration:

bclr PACTL,$42 ; disable 16-bit PACA, disable overflow interrupt

bclr PBCTL,$42 ; disable 16-bit PACB, disable overflow interrupt

movb #$44,TCTL4 ; select the rising edges as active edge

bset ICPAR,$0A ; enable PAC3 and PAC1

bclr DDRT,$0A ; configure PT3 and PT1 for input

▲

8.8 Modulus Down Counter

The HCS12 timer system contains a modulus down counter that can be used as a time
base to generate periodic interrupts. It can also be used to latch the value of the IC registers
and the pulse accumulators to their holding registers. The action of latching can be periodic or
only once.
The modulus down counter has a prescaler, which divides the E-clock and uses its output
as the clock input to the down counter. The prescaler can be 1, 4, 8, and 16. The operation of
the modulus down counter is controlled by the MCCTL register. The MCFLG register records
the status of the modulus down counter. The contents of the MCCTL and MCFLG registers are
shown in Figures 8.32 and 8.33, respectively.