Timer Functions - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 369

8.5.2 Pins for Input-Capture
Port T has eight signal pins (PT7,PT0) that can be used as input-capture/output-compare or
general I/O pins. PT3,PT0 can also be used as the pulse accumulator input (PA3,PA0). The user
must make sure that the PT3,PT0 pins are enabled for one and only one of these three functions
( OCn, ICn, and PAn ). When these pins are not used for timer functions, they can also be used as
general-purpose I/O pins. When being used as general I/O pins, the user must use the DDRT reg-
ister to configure their direction (input or output). When a Port T pin is used as a general-purpose
I/O pin, its value is reflected in the corresponding bit in the PTT register.
8.5.3 Registers Associated with Input-Capture
The user needs to specify what signal edge to capture. The edge selection is done via the
Timer Control registers 3 and 4, as shown in Figure 8.6.

7 6 5 4 3 2 1 0

EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A

Reset:

0 0 0 0 0 0 0 0

(a) Timer control register 3 (TCTL3)

7 6 5 4 3 2 1 0

EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A

Reset:

0 0 0 0 0 0 0 0

(b) Timer control register 4 (TCTL4)

EDG n B EDG n A: Edge configuration ( n = 0, , 7)

. . .

0 0 : capture disabled
0 1 : capture on rising edges only
1 0 : capture on falling edges only
1 1 : capture on both edges

Figure 8.6 ■ Timer Control registers 3 and 4

When an input-capture channel is selected but capture is disabled, the associated pin can
be used as a general-purpose I/O pin.
An input-capture channel can optionally generate an interrupt request on the arrival of a
selected edge if it is enabled. The enabling of an interrupt is controlled by the Timer Interrupt
Enable register (TIE). The enabling of input-capture 7 through input-capture 0 interrupt is con-
trolled by bit 7 through bit 0 of TIE. When a selected edge arrives at the input-capture pin, the
corresponding flag in the Timer Flag register 1 (TFLG1) is set. The contents of TIE and TFLG1
are shown in Figures 8.7 and 8.8, respectively.

7 6 5 4 3 2 1 0

C7I C6I C5I C4I C3I C2I C1I C0I

Reset: 0 0 0 0 0 0 0 0

C7I:C0I: input-capture/output-compare interrupt enable bits
0 = interrupt disabled
1 = interrupt enabled

Figure 8.7 ■ Timer Interrupt Enable register (TIE)