Hardware Reference
In-Depth Information
The main function of the RTI circuit is to generate hardware interrupts periodically. If
enabled, this interrupt will occur at the rate selected by the RTICTL register. The contents of
this register are shown in Figure 6.16. The possible interrupt periods (in number of OSCCLK
cycles) are listed in Table 6.4.
The time-multiplexing technique has been used to display multiple seven-segment displays
at the same time in Chapter 4. However, the method used in Chapter 4 requires the CPU to call
a delay function to generate the desired time delay to switch the digit to be displayed; this would
prevent the CPU from performing other operations. One solution to this problem is to remind the
CPU to switch digits to be displayed periodically. The RTI function serves this purpose perfectly
well. The next three examples use the RTI program to perform seven-segment pattern shifting.
7
6
5
4
3
2
1
0
RTR0
0
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
Reset:
0
1
0
0
0
0
0
0
Figure 6.16
■
CRG RTI control register (RTICTL)
RTR[6:4]
RTR[3:0]
000
(off)
001
(2
10
)
010
(2
11
)
011
(2
12
)
100
(2
13
)
101
(2
14
)
110
(2
15
)
111
(2
16
)
0000 (
4
1)
0001(
4
2)
0010 (
4
3)
0011 (
4
4)
0100 (
4
5)
0101 (
4
6)
0110 (
4
7)
0111 (
4
8)
1000 (
4
9)
1001 (
4
10)
1010 (
4
11)
1011 (
4
12)
1100 (
4
13)
1101 (
4
14)
1110 (
4
15)
1111 (
4
16)
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
off*
2
10
2
3
2
10
3
3
2
10
4
3
2
10
5
3
2
10
6
3
2
10
7
3
2
10
8
3
2
10
9
3
2
10
10
3
2
10
11
3
2
10
12
3
2
10
13
3
2
10
14
3
2
10
15
3
2
10
16
3
2
10
2
11
2
3
2
11
3
3
2
11
4
3
2
11
5
3
2
11
6
3
2
11
7
3
2
11
8
3
2
11
9
3
2
11
10
3
2
11
11
3
2
11
12
3
2
11
13
3
2
11
14
3
2
11
15
3
2
11
16
3
2
11
2
12
2
3
2
12
3
3
2
12
4
3
2
12
5
3
2
12
6
3
2
12
7
3
2
12
8
3
2
12
9
3
2
12
10
3
2
12
11
3
2
12
12
3
2
12
13
3
2
12
14
3
2
12
15
3
2
12
16
3
2
12
2
13
2
3
2
13
3
3
2
13
4
3
2
13
5
3
2
13
6
3
2
13
7
3
2
13
8
3
2
13
9
3
2
13
10
3
2
13
11
3
2
13
12
3
2
13
13
3
2
13
14
3
2
13
15
3
2
13
16
3
2
13
2
14
2
3
2
14
3
3
2
14
4
3
2
14
5
3
2
14
6
3
2
14
7
3
2
14
8
3
2
14
9
3
2
14
10
3
2
14
11
3
2
14
12
3
2
14
13
3
2
14
14
3
2
14
15
3
2
14
16
3
2
14
2
15
2
3
2
15
3
3
2
15
4
3
2
15
5
3
2
15
6
3
2
15
7
3
2
15
8
3
2
15
9
3
2
15
10
3
2
15
11
3
2
15
12
3
2
15
13
3
2
15
14
3
2
15
15
3
2
15
16
3
2
15
2
16
2
3
2
16
3
3
2
16
4
3
2
16
5
3
2
16
6
3
2
16
7
3
2
16
8
3
2
16
9
3
2
16
10
3
2
16
11
3
2
16
12
3
2
16
13
3
2
16
14
3
2
16
15
3
2
16
16
3
2
16
* Denotes the default value out of reset. This value disables RTI.
Table 6.4
■
RTI period (in units of OSCCLK cycle)
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