Interrupts, Clock Generation, Resets, and Operation Modes - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 286

movb #$60,PLLCTL ; disable clock monitor, enable PLL, set automatic

; bandwidth control, disable RTI and COP in pseudo-stop

brclr CRGFLG,LOCK,* ; wait until PLL locks into the target frequency

rts

The C language version of the function is as follows:
void SetClk8 (void)
{

SYNR

5 0x02;

// use PLL and 4-MHz crystal to generate 24-MHz system clock

REFDV

5 0;

// “

CLKSEL

5 0x80;

// enable PLL, keep SYSCLK running in wait mode

PLLCTL

5 0x60;

// enable PLL, set automatic bandwidth control

while (!(CRGFLG & 0x08)); // wait until PLL locks into the target frequency

}

In addition to this instruction sequence, we also need to tie the XCLKS pin to ground to bypass
the crystal oscillator.

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Example 6.3
▼

There is a system that uses a 4-MHz crystal oscillator to derive a 24-MHz E-clock. Write a
subroutine to perform the required configuration.
Solution: The frequency of SYSCLK would be 48 MHz. The frequencies of OSCCLK and
PLLCLK are 4 MHz and 48 MHz, respectively. According to Equation 6.1,
48 MHz 5 2 3 4 MHz 3 [SYNR 1 1]/[REFDV 1 1]
One of the alternatives could be to set SYNR and REFDV to 5 and 0, respectively. The following
subroutine achieves the desired configuration:
SetClk4

movb #$05,SYNR ; set SYNR to 5

movb #$0,REFDV ; set REFDV to 0

movb #$80,CLKGSEL ; enable PLL, keep SYSCLK running in wait mode,

; keep RTI, COP, PLL, and core running in wait mode

movb #$60,PLLCTL ; disable clock monitor, enable PLL, set automatic

; bandwidth control, disable RTI and COP in pseudo-stop

brclr CRGFLG,LOCK,* ; wait until PLL locks into the target frequency

rts

We also need to pull the XCLKS pin to high to select the crystal oscillator to generate the
OSCCLK signal.

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6.6.6 Clock Monitor
The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay so that it can
operate without any MCU clocks. If no OSCCLK edges are detected within this RC time delay, the
clock monitor indicates failure; this asserts self-clock mode or generates a system reset depending on
the state of the SCME bit. If the clock monitor is disabled or the presence of clocks is detected, no
failure is indicated. The clock monitor function is enabled or disabled by the CME control bit.