Biomedical Engineering Reference
In-Depth Information
Fig. 8
Schematic of the other building blocks:
a
Integrator.
b
Delay generator
Fig. 9
System-on-a-Chip
(SoC) ultra-wideband (UWB)
pulse radar.
a
Micrograph of
the radar testchip (all pads are
ESD protected). The die size
is 1.5
1.3 mm
2
(including
the multiplier as stand-alone
device).
b
Radar testchip
packaged in a QFN32
leadless package (
bottom
view
) with exposed ground
pad (size 5
×
5mm
2
)
×
The receiver and transmitter of the SoC UWB pulse radar have been designed
in order to have inputs and outputs on the two opposite sides of the die, allowing a
straight connection to the input and output pins of the package, and then with the
two planar antennas realized on FR4 board as reported hereinafter.
On-chip characterization of the SoC UWB pulse radar has been carried out by
means of GSGSG Infinity probes by Cascade
®
. A test-board in FR4 for supplying
DC and control voltages to the radar test-chip has been designed and realized. The
testchip has been attached to the board; DC and control voltages have been bonded to
the board. The measurement setup is shown in Fig.
10
. The PG output is connected
to the LNA input by means of microprobes, cables and attenuators. The propagation
delay of cables and attenuators has been derived from their measured S-parameters
[
19
] and amounts to about 8 ns.
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