Biomedical Engineering Reference
In-Depth Information
Fig. 7 I/O signals of the
multiplier measured in three
cases: the input monocycle
pulses have a no relative
delay (i.e., time alignment),
b a relative delay of half of
the time duration, and c
relative delay equal to the
time duration. V O is captured
by means of the probe 1134A
(impedance 50 K ||0.27 pF)
and oscilloscope DSO
54855A
This circuit solution allows us to implement efficiently the multiplication between
short pulses.
The schematic of the integrator is shown in Fig. 8 a. The integrator consists of
a 3-stage amplifier with Resistive-Capacitive (RC) feedback and output buffer. The
stages use identical differential pair amplifiers. Details of the devices sizing are
reported by Zito et al. [ 13 ]. The power consumption is 1.1 mW. The voltage gain is
58 dB and B 3dB is equal to 147 Hz.
The schematic of the 5-bit programmable monotonic DG is shown in Fig. 8 b. It has
been designed following the principle explained by Maymandi-Nejad and Sachdev
[ 18 ]. Details of the devices sizing are reported by Zito et al. [ 13 ]. The 5 bits allow us
to select the output current of the inverter (M 8 and M 9 ) in order to vary the slope of
the voltage ramp (high to low) on its load capacitance. By varying the bias current,
the DG can provide delays in the range 1-30 ns. The power consumption is lower
than 0.1 mW.
System-on-a-Chip Ultra-Wideband Pulse Radar
The micrograph of the radar microchip is shown in Fig. 9 . The die area amounts to
about 2 mm 2 . The overall power consumption amounts to 73.2 mW.
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