Cryptography Reference
In-Depth Information
Figure 9.12 - Different positions of the interconnection network obtained by processing
the parity nodes in the Fourier domain. These positions separate those parts of the
iteration to be performed in the VNP from those performed in the PNP.
Position of the network
1
2
3
4
f
−
1
f
−
1
VNP
Σ
f
◦
Σ
Σ
◦
f
◦
Σ
◦
f
−
1
◦
Σ
◦
f
f
−
1
◦
Σ
Σ
◦
f
Σ
PNP
Fourier
module
Direct
PNP sign
Product of the signs
Table 9.2 - Value of the generic operator associated with the variable processors
(VNPs) and parity processors (PNPs) as a function of the position of the intercon-
nection network.
This architecture is composed of
P
PNPs which each generate
d
=
d
p
mes-
sages in
α
p
clock cycles. These processors therefore have
d
c
=
d
c
/α
p
inputs
and outputs. They are connected to an interleaving network that is direct and
inverse. On the other side of this interleaving network are placed
Pd
p
/d
v
VNPs. These processors similarly generate
d
=
d
v
messages in
α
v
clock cycles,
and therefore have
d
v
=
d
v
/α
v
inputs and outputs.
The degree of parallelism of the architecture is defined by the three parame-
ters
P
,
α
p
and
α
v
. It is possible to obtain all the degrees of parallelism possible,
ranging from the completely parallel architecture where
P
=
m
,
α
p
=1
and
α
v
=1
to the completely serial architecture where
P
=1
,
α
c
=
d
c
and
α
v
=
d
v
.
Note that such an architecture has a computing power (equation (9.30))
P
c
=
P
d
c
.
Direct inverse interleaving networks enable the messages associated with the
different VNPs to be routed towards different PNPs and vice-versa. This kind
of network generally makes it possible to perform several permutations, called
space permutations. Another type of permutation, called a time permutation,
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