Graphics Reference
In-Depth Information
a
b
Fig. 10.24
Logic and SRAM utilization for each processing engine. (
a
) Logic utilization in kgates
(total 715 kgate). (
b
) SRAM utilization in kbits (total 1,018 kbit)
Fig. 10.25
Relative power consumption of processing engines and SRAMs from post-layout
simulation with bi-prediction
that the MC cache takes up a significant portion of the total power. However, the
DRAM power saving due to the cache is about six times the cache's own power
consumption.
Tab le
10.15
shows the comparison with state-of-the-art video decoders. We
observe that the 2
compression efficiency of HEVC comes at a proportionate cost
in logic area. The SRAM utilization is much higher due to larger coding units and
use of on-chip line-buffers.
10.10
Conclusion
This chapter presented the key challenges in implementing a hardware decoder
for HEVC and techniques to address the challenges. The architecture of a test
chip was described in detail. The test chip uses a variable-sized split system
