Graphics Reference
In-Depth Information
Chapter 10
Decoder Hardware Architecture for HEVC
Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze,
and Anantha Chandrakasan
Abstract
This chapter provides an overview of the design challenges faced in the
implementation of hardware HEVC decoders. These challenges can be attributed to
the larger and diverse coding block sizes and transform sizes, the larger interpolation
filter for motion compensation, the increased number of steps in intra prediction
and the introduction of a new in-loop filter. Several solutions to address these
implementation challenges are discussed. As a reference, results for an HEVC
decoder test chip are also presented.
10.1
Introduction
HEVC presents several new challenges for a hardware decoder implementation.
HEVC's decoding complexity is found to be between 1:4
and 2
of H.264/AVC
[
22
] when measured in terms of cycle count for software. In hardware, however, the
increased complexity of HEVC entails significant increase in hardware cost over
traditional H.264/AVC decoders, both at the top-level of the video decoder, and in
the low-level processing blocks. Some of the challenges are listed below.
The diverse sizes of Coding Tree Units (CTU), Coding Units (CU), Prediction
Units (PU) and Transform Units (TU) require complex state machines to control
the system pipeline and data paths in the individual processing blocks.
Thelarge tCTU 64
64)is16
larger than the H.264/AVC macroblock (16
16), which means that the memories in pipeline stages need to be proportionately
larger.
M. Tikekar (
) C. Juvekar V. Sze A. Chandrakasan
Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, MA 02139, USA
e-mail:
mtikekar@mit.edu
C.-T. Huang
National Tsing Hua University, Hsinchu, Taiwan
