Real-Time Error Recovery Using a Compact Dictionary - Hardware/Software Co-Design and Optimization for Cyberphysical Integration in Digital Microfluidic Biochips - page 76

element in the original actuation matrix is n b bits. In the de-compaction module, the
de-compacted M N actuation sub-matrix will be stored in an .M N n b /-bit
register. Before applying the actuation matrix on the electrodes of the biochip, the
data stored in the .M N n b /-bit register is reset to zero. Next the de-compaction
module “fills” non-zero elements into the .M N n b /-bit register, i.e., the module
assigns the elements in the 1 vector to the .M N n b /-bit register. When

the de-compaction procedure of one M N actuation sub-matrix is finished, the
corresponding actuation signals are applied to electrodes on the biochip. The data
stored in the .M N n b /-bit register will be reset to zero again, and the next
segment in the compacted actuation matrix will be de-compacted.
The compaction results derived from Method II can be restored to the original
actuation matrix in a similar way.
The clock frequency of the biochip is usually between 1 and 100 Hz, i.e., moving
a droplet from one electrode to the adjacent electrode takes 10 ms to 1 s [ 25 ]. On the
other hand, clock frequency for de-compaction and writing data into the .M N
n b /-bit register can be as high as 16 MHz [ 17 ]. The frequency of the FPGA is several
orders of magnitudes higher than the frequency of fluid-handling operations, hence
the total time needed for accessing the dictionary, de-compaction, and transfer of
data from the FPGA to buffers in the peripheral circuit is negligible compared to the
operation time of the biochip.

K

3.6 Implementation of Dictionary-Based Error Recovery

on FPGA

The circuitry for error recovery on a cyberphysical microfluidic biochip consists
of four main modules, i.e., (1) the sensing module for the detection of errors, (2)
the memory module for the storage of the error dictionary, (3) the FSM module for
the dynamic adjustment of actuation sequences when errors occur, and (4) the de-
compaction module for decoding the actuation matrices. All four modules can be
implemented on an FPGA.
The modules are described using Verilog, and synthesized using Quartus
II [ 28 ]. All functional and timing simulations for the modules are performed using
ModelSim-Altera [ 29 ]. The FPGA used in the simulation belongs to the family of
Cyclone IV [ 30 ], which includes a series of devices. The maximum numbers of
I/O ports and logic elements provided by these devices are different [ 30 ]. While
synthesizing the modules, Quartus II automatically selects the suitable devices
based on the required number of I/O ports and logic elements. The maximum
on-chip memory that the family of Cyclone IV can provide is 0.83 MB.
The interconnection of the modules is presented in Fig. 3.5 , and the detailed
implementation of these modules in an FPGA is discussed below.