Design of the Dynamic Supply CMOS RF Power Amplifie - Linear CMOS RF Power Amplifiers for Wireless Applications - page 28

The maximum output power can finally be expressed as a function of the opti-
mum resistance as

I max R opt
8

P out _ max = . (3.18)

The equations above can be used to determine the optimum resistance and max-
imum drain current for a given maximum output power. Conversely, they can also
be used to determine the maximum output power for given I max and R opt .
A first size for the transistor can be obtained from the equation for the drain
current of a MOS transistor in saturation [ 16 , Chap. 1]:

μC ox
2

W
L (V GS −

V T ) 2 . I d = (3.19)

With I d = I max and choosing the minimum dimension for the channel length, the
width of the transistor can be determined.
Figure 3.11 shows that the quiescent drain voltage of the transistor is V DC =
VDD due to the presence of the RF choke inductor. Since the output voltage signal
is symmetric with respect to VDD, the output swing is limited either by V knee or
by V BR . Generally, in submicron CMOS technologies, the knee voltage is more re-
strictive than the breakdown voltage and is the limiting factor for achieving a higher
output power for a given transistor size. Furthermore, V knee varies not only with
I max , but also with the width of the transistor. If we consider that the knee voltage is
more stringent than the breakdown voltage, that is, V DC −

V knee <V BR −

V DC , and
that the maximum output power is known, we can use the following procedure to
size the output stage of a class A power amplifier:

1. Make a first guess for V knee and calculate I DC using ( 3.11 ).
2. Calculate W using ( 3.19 ) and I d = 2 I DC . V GS must be chosen according

to the output swing of the previous amplifying stage. If there is no constraint
regarding the swing of the signal that will be available at the gate of the transistor,
the choice of V GS can be done based on simulation—see item 4).
3. Simulate the transfer characteristics of the transistor to check the value of the
knee voltage.
4. With the new V knee , return to the first point. If the value of V knee is correct,
calculate R opt using ( 3.15 )-( 3.17 ).
If V knee is too high, other values for W can be simulated to find an optimum
transistor size for which the maximum output power is attained with a min-
imum I max . Care must be taken at this point because the optimum size for
minimum power consumption is not necessarily the optimum size for mini-
mum distortion. A trade-off must be made.

I max =

The core of the dynamic supply RF power amplifier is shown in Fig. 3.13 .Two
pads are used for the RF ground (RF GND), two for the RF input (RFIN), two for
the RF output (RFOUT), and one for the gate bias ( V bias ). An off-chip inductor that
plays the role of the RF choke is also used and is connected to the RFOUT pin.
The impedance matching networks are implemented with external components on