Design of the Dynamic Supply CMOS RF Power Amplifie - Linear CMOS RF Power Amplifiers for Wireless Applications - page 26

Fig. 3.11 Basic CMOS
power amplifier circuit

caution [ 12 , Chap. 4]. The use of a switched-mode PA in a dynamic supply system
was reported in [ 29 ], but, in that case, the use of digital predistortion was necessary.
The basic structure of a linear CMOS RF PA is shown in Fig. 3.11 . There are two
important building blocks that can be distinguished: the power amplifying stage and
the impedance matching network. Besides, an RF choke is used to provide a DC
path for the current coming from the power supply with a very high impedance at
RF frequencies. The DC block (or AC coupling) capacitors prevent the input and
output terminations of the power amplifier from disturbing its DC operating point.
Although Fig. 3.11 depicts a single-stage amplifier, 2-stage [ 7 , 19 ] and 3-stage
[ 13 , 30 ] PAs are common in CMOS designs due to the low power gain of a single
stage.

3.3.1 Design Procedure

The sizing of the output-stage of a linear PA depends on the maximum current ( I max )
that the transistor must be able to provide and on two technology-dependent param-
eters: the breakdown ( V BR ) and knee ( V knee ) voltages. The maximum current is
calculated from the maximum output power ( P out _ max ) that the PA must deliver to
the load. The load is the optimum resistance ( R opt ) obtained after the transformation
of the antenna impedance. This transformation is provided by the output matching
network.
The optimum resistance can be calculated using the loadline method described
in [ 12 , Chap. 1]. Figure 3.12 illustrates the application of this method for a MOS
transistor with an idealized transfer characteristic. The knee voltage, as shown in
Fig. 3.12 , is the turn-on voltage of the transistor [ 12 , Chap. 2] separating the sat-
uration region from the linear region—also known as ohmic or triode region. The
breakdown voltage is the drain voltage at which the drain current begins to increase
at a much higher rate than in the saturation region. For voltages higher than V BR ,
a drain-substrate junction breakdown may occur [ 16 , Chap. 1].
From Fig. 3.12 , a set of equations to calculate R opt can be derived. From the V DS
and I DS curves, the maximum output power is

(V DC − V knee ) × I DC

P out _ max = . (3.11)

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