Design of the Dynamic Supply CMOS RF Power Amplifie - Linear CMOS RF Power Amplifiers for Wireless Applications - page 21

Fig. 3.5 Fully-differential comparator circuit

When the amplitude of the input error signal increases, the output of the linear
stages starts slewing. Hence, a minimum size is used for the first inverter to decrease
the capacitive load seen by the third pre-amplifying stage. The two inverter stages
used provide a rail-to-rail output signal and a better slew rate by gradually increasing
the load capacitance. Furthermore, their class B operation minimizes the current
consumption.
The complete comparator circuit depicted in Fig. 3.5 includes the component
dimensions. The three DC current sources ( I b1 = 5µA)are

implemented off-chip so that they can be adjusted during the characterization of the
circuit. The node v casc is accessible through a pad for debugging purposes.

I b2 = 100 µA and I b3 =

3.2.2 Synchronous Switch

The standard structure of a buck or step-down converter is shown in Fig. 3.6 (a),
where V batt is the supply voltage of the modulator, which in our case equals VDD.
The forward voltage of the freewheeling diode when the switch S is off limits the ef-
ficiency of the converter [ 20 , Chap. 3]. By replacing the diode D by another switch,
S 2 , as shown in Fig. 3.6 (b), the efficiency of the converter can be increased if the
switch is designed for low losses. In the case of a MOS implementation, the on
resistance of the transistor, which must be minimized, is given by ( 3.2 ).

L

r on = . (3.2)

μC ox
2

W(V GS − V T − V DS )