Design of the Dynamic Supply CMOS RF Power Amplifie - Linear CMOS RF Power Amplifiers for Wireless Applications - page 20

Fig. 3.4 Fully-differential comparator block diagram

3.2.1 High-Speed Comparator

The delay of the modulator chain is dominated by the comparator delay. The com-
parator delay can be decreased by using a high-speed comparator architecture in
which a good trade-off between speed and power consumption is made. The design
of high-speed comparators is well covered in [ 6 , Chap. 8]. Figure 3.4 depicts the
block diagram of the comparator designed for the dynamic supply modulator. We
followed the same configuration of [ 28 , Chap. 6], wherein further implementation
details can be found. Figure 3.4 indicates that three pre-amplifying stages and two
inverter stages are used. A Common-Mode FeedBack (CMFB) control is necessary
because the pre-amplifying stages are fully-differential.
For small signals around the switching point, the input error signal has a higher
amplitude after each amplifying stage, but after passing the three first stages the
signal is still small so that we can assume linear operation at these stages. Each
cascaded stage contributes to a certain propagation delay which is related to the
frequency response of the stage. If we consider a single-pole frequency response,
this delay can be decreased by reducing the capacitance associated to the node of
highest impedance. Figure 3.5 shows the complete schematic of the comparator and
these high-impedance nodes are those at the output of the three differential pairs
used in the three first stages. Hence, to reduce the capacitance at these nodes we
adopted cascode differential pairs with resistive loads, followed by common-drain
structures before driving the subsequent stages. The purpose of using three stages
is to amplify the error signal gradually so that a high gain can be achieved with
a good frequency response. The gain determines the minimum required amplitude
of the signal at the input so that the output of the comparator switches states. If
we consider that the input signal has a finite slope, a low minimum input signal
amplitude and, therefore, a high gain, decreases the delay introduced by the slope
of the input signal [ 28 , (6.6)].