Digital Signal Processing Reference
In-Depth Information
Table 10.2
Required values
of source and load
impedances for simultaneous
conjugate match and
corresponding maximum gain
at 5.2 GHz
Parameter
Value
Z
MS
()
8
−
i47
.
4
Z
ML
()
9
.
4
−
i43
.
3
G
max
(dB)
9.1
power gain under simultaneous conjugate match is calculated using
S
trl
and the
expression below [
17
].
S
21
.
2
1
1
−|
Γ
ML
|
G
max
=
(10.7)
2
2
1
−|
Γ
MS
|
|
1
−
S
22
Γ
ML
|
Table
10.2
shows the values found after applying (
10.3
)-(
10.7
) to the S parame-
ters of the TRL measurement at 5.2 GHz.
The maximum theoretical gain is 9.1 dB. Comparing to the measured unmatched
power gain of 2.4 dB given in Table
10.1
, there is a large improvement margin to be
exploited through impedance matching.
The embedding network model developed previously allows one to determine
the value and position of shunt capacitors that can be added to the microstrip ac-
cess lines to attain the source and load impedance values of Table
10.2
. This can be
done before physically placing the capacitors on the board, avoiding trial-and-error
impedance matching implementation. The Smith chart can be very useful in the de-
termination of the position and value of these capacitors. The software Smith Chart
presented in [
25
], whose demo version can be downloaded from [
11
], is used in this
example for this purpose. By choosing the frequency of interest and beginning from
the 50
impedance of the network analyzer ports, the change to this impedance
caused by the embedding networks can be traced on a Smith chart for every micron
of the transmission lines. This gives the designer the ability to exactly know where
to place the chip capacitors and which values must be chosen.
10.3.5.1 Matching the Output
The departing point is 50
and the objective is to transform it in the desired load
impedance given in Table
10.2
:
Z
ML
=
−
i43
.
3 at 5.2 GHz. Using the Smith
Chart tool and referring to Fig.
10.10
, the departing point is marked as number
1
.
Then, the pieces of transmission line that compose the output embedding network
are added according to the model of Fig.
10.7
.
2
Point
2
is superposed to Point
1
because the SMA connector between these two points was modeled as a 50
line
with an electrical delay. Point
4
is superposed to Point
3
because the 50
microstrip
line between these two points has a length of
λ/
2 and, hence, it provides a complete
turn around the center of the Smith chart. The impedance of 44
.
5
9
.
4
−
i7
.
5
at point
4
is the load impedance seen by the unmatched power amplifier.
2
In this example, without loss of accuracy, the step discontinuities in the microstrip line model
were considered to be lossless when using the Smith Chart software.
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