Hardware Reference
In-Depth Information
Exercise 3.11: Need for Reset #2
This exercise concerns the parity detector of i gure 5.5c, which has a data-valid (
dv
)
input. Assume that a reset input is not provided and that the circuit is implemented
in a device whose l ip-l ops' initial state (on power-up) is arbitrary.
a) If the initial state falls
inside
the machine (in state
zero
,
one
, or
hold_one
), will the
circuit operate properly? Does this answer depend on the encoding scheme?
b) Answer the same questions above for the case when the initial state falls
outside
the machine.
c) Prove that this FSM works well in both cases mentioned above if sequential encod-
ing is used and optimal (minimal) expressions are used for
nx_state
(
d
1
,
d
0
).
d) Prove that it also works well in both cases mentioned above if one-hot encoding
is used and optimal (minimal) expressions are used for
nx_state
(
d
2
,
d
1
,
d
0
).
e) Consider that sequential encoding is used. Show that if the “don't care” bits are all
i lled with '0's the machine is not subject to deadlock, but if they are all i lled with
'1's then deadlock can occur.
f) Consider now that one-hot encoding is used. Show that in both cases (“don't care”
bits all i lled with '0's or all i lled with '1's) deadlock can occur.
Suggestion to solve parts c and d: First, review sections 3.8 and 3.9; next, use the
method seen in section 3.3 to i nd the machine's optimal expressions for
nx_state
;
then apply the values of
pr_state
(i.e.,
q
1
and
q
0
in c or
q
2
,
q
1
, and
q
0
in d) and of the
transition conditions (
dv
and
x
) for the cases not used in the FSM encoding (states
outside
the machine) to the expressions derived to show that the results always con-
verge to states
inside
the machine.
Exercise 3.12: Capturing the First Bit
Two options for processing data correctly when the i rst data bit is made available at
the same time that the data-valid (
dv
) bit is asserted were presented in i gure 3.16.
Show that the option in i gure 3.16c will no longer work if the auxiliary register that
stores
x
operates at the falling clock edge.
Exercise 3.13: Storing the Final Result
Explain why the option in i gure 3.18 is better than any of the options in i gure 3.17
for registering a process's i nal result.
Exercise 3.14: Multimachine Design
In i gure 3.20a, an FSM with a repetitive pair of states is shown, for which a solution
using two FSMs was presented in i gure 3.20b. Complete the timing diagrams of i gure
3.28 for the machines of i gure 3.20b, assuming that
T
= 3.
