Hardware Reference
In-Depth Information
Figure 15.3
Simulation results from the VHDL code for the serial data transmitter of i gure 15.2.
Figure 15.4
(a) Serial data receiver of i gure 3.16c. (b) Adapted version for pointer-based implementation.
four consecutive bits received at input
x
(hence, this is a timed machine, with
t
running from 0 to 3—a small range was adopted in order to ease the inspection of
the simulation results). Because it is assumed that the i rst data bit is made available
at the same time that
dv
is asserted (both updated at the positive clock edge), which
is more difi cult to detect, one must be careful with respect to the clock edges (see
rectangle in the upper part of the i gure and also the discussion in section 3.10). This
machine is simple enough to be implemented using the pointer-based approach, for
which an adapted state diagram is presented in i gure 15.4b. Note that the counter
(pointer) must run from 0 to 4. Again, care must be taken with respect to the clock
edges.
A VHDL code for the machine of i gure 15.4b is presented below. It contains just
one process, which builds the pointer (lines 19-27) and the
registered
LUT (lines 30-35).
Because
x
must be stored (producing
y
) in a deserializer, the
case
statement (lines
31-34) was placed inside an
if rising_edge(clk)
statement (lines 30 and 35), which is
responsible for inferring l ip-l ops.
1 -------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 -------------------------------------------------
5 entity serial_receiver is
6
port (
7
x, dv, clk, rst: in std_logic;
8
y: buffer std_logic_vector(3 downto 0));
