Hardware Reference
In-Depth Information
11 READ_opcode: std_logic_vector(7 downto 0) := "00000011";
12
initial_addr_for_wr: std_logic_vector(15 downto 0) := (others=>'0');
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initial_addr_for_rd: std_logic_vector(15 downto 0) := (others=>'0'));
14 --Assumed: fclk=50MHz, desired SPI speed=5MHz
15 port (
16 --System ports:
17 rd, wr, clk, rst: in std_logic;
18 ssd1, ssd2: out std_logic_vector(6 downto 0);
19 --SPI ports:
20 SCK, SSn, MOSI, WPn, HOLDn: out std_logic;
21 MISO: in std_logic);
22 end entity;
23 ----------------------------------------------------------------
24 architecture moore_fsm of FRAM_with_SPI_bus is
25
26
--FSM-related declarations:
27
type state is (idle, WREN, deselect, WRITEx, initial_addr_wr,
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wr_data, wait_wr0, READx, initial_addr_rd, rd_data, wait_rd0);
29
signal pr_state, nx_state: state;
30
31
--Timer-related declarations:
32
signal i, imax: natural range 0 to 15;
33
signal j, jmax: natural range 0 to 7;
34
35
--SPI clock and test signal declarations:
36
signal spi_clk: std_logic;
37
type data_array is array (0 to 7) of std_logic_vector(7 downto 0);
38
constant data_out: data_array :=
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("00000001", "00100011", "01000101", "01100111",
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"10001001", "10101011", "11001101", "11101111");
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signal data_in: data_array;
42
43 begin
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WPn <= '1';
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HOLDn <= '1';
47
48
--Generate 5MHz clock for SPI circuit:
49
process (clk)
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variable counter1: natural range 0 to 5;
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begin
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if rising_edge(clk) then
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counter1 := counter1 + 1;
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if counter1=5 then
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spi_clk <= not spi_clk;
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counter1 := 0;
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end if;
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end if;
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end process;
60
61
--Timers (using strategy #1):
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process (spi_clk, rst)
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begin
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if (rst='1') THEN
